SNAS449F February   2008  – May 2017 DAC081C081 , DAC081C085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifier
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Power-On Reset
      5. 8.3.5 Simultaneous Reset
      6. 8.3.6 Additional Timing Information: toutz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Basic I2C Protocol
      3. 8.5.3 Standard-Fast Mode
      4. 8.5.4 High-Speed (Hs) Mode
      5. 8.5.5 I2C Slave (Hardware) Address
      6. 8.5.6 Writing to the DAC Register
      7. 8.5.7 Reading from the DAC Register
    6. 8.6 Registers
      1. 8.6.1 DAC Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
      2. 9.1.2 DSP/Microprocessor Interfacing
        1. 9.1.2.1 Interfacing to the 2-Wire Bus
        2. 9.1.2.2 Interfacing to a Hs-mode Bus
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1 Specification Definitions
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

For best accuracy and minimum noise, the printed-circuit-board containing the DAC081C081 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located on the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will use a fencing technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be used when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC081C081. Special care is required to ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces.

The DAC081C081 power supply should be bypassed with a 4.7-µF and a 0.1-µF capacitor as close as possible to the device with the 0.1 µF right at the device supply pin. The 4.7-µF capacitor should be a tantalum type and the 0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC081C081 should only be used for analog circuits.

Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. These clock and data lines should have controlled impedances.

11.2 Layout Example

DAC081C081 DAC081C085 layout_example_SNAS449.gif Figure 35. Typical Layout