ZHCSB79A August   2013  – August 2014 CSD95375Q4M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Powering CSD95375Q4M And Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Curves (SOA)
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss and SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 商标
    2. 10.2 静电放电警告
    3. 10.3 术语表
  11. 11机械封装和可订购信息
    1. 11.1 机械制图
    2. 11.2 建议印刷电路板 (PCB) 焊盘图案
    3. 11.3 建议模板开口

封装选项

机械数据 (封装 | 引脚)
  • DPC|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings (1)

TA = 25°C (unless otherwise noted)
VALUE UNIT
MIN MAX
VIN to PGND –0.3 20 V
VSW to PGND , VIN to VSW –0.3 20 V
VSW to PGND, VIN to VSW (<10 ns) –7 23 V
VDD to PGND –0.3 6 V
PWM, SKIP# to PGND –0.3 6 V
BOOT to PGND –0.3 25 V
BOOT to PGND (<10 ns) –2 28 V
BOOT to BOOT_R –0.3 6 V
BOOT to BOOT_R (duty cycle <0.2%)
ESD Rating Human Body Model (HBM) 2000 V
Charged Device Model (CDM) 500 V
Power Dissipation, PD 8 W
Operating Temperature Range, TJ –40 150 °C
Storage Temperature Range, Tstg –55 150 °C
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
Gate Drive Voltage, VDD 4.5 5.5 V
Input Supply Voltage, VIN 16 V
Continuous Output Current, IOUT VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH(1)		 25 A
Peak Output Current, IOUT-PK(2) 60 A
Switching Frequency, ƒSW CBST = 0.1 µF (min) 2000 kHz
On Time Duty Cycle 85%
Minimum PWM On Time 40 ns
Operating Temperature –40 125 °C
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 10 ms, duty cycle ≤1%

6.3 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance (Top of package)(1) 22.8 °C/W
RθJB Junction-to-Board Thermal Resistance(2) 2.5
(1) RθJC is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches,
0.06-inch (1.52-mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1-mm of the package.

6.4 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power Loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.2 W
Power Loss(2) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 2.6 W
VIN
VIN Quiescent Current, IQ PWM=Floating, VDD = 5 V, VIN= 14.5 V 1 µA
VDD
Standby Supply Current, IDD PWM = Float, SKIP# = VDD or 0 V 130 µA
SKIP# = Float 8 µA
Operating Supply Current, IDD PWM = 50% Duty cycle, ƒSW = 500 kHz 6.4 mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising 4.15 V
UVLO, VDD Falling 3.7 V
Hysteresis 0.2 mV
PWM and SKIP# I/O Specifications
Input Impedance, RI Pull Up to VDD 1700 kΩ
Pull Down (to GND) 800
Logic Level High, VIH 2.65 V
Logic Level Low, VIL 0.6
Hysteresis, VIH 0.2
Tri-State Voltage, VTS 1.3 2
Tri-state Activation Time (falling) PWM, tTHOLD(off1)(2) 60 ns
Tri-state Activation Time (rising) PWM, tTHOLD(off2)(2) 60
Tri-state Activation Time (falling) SKIP#, tTSKF(2) 1 µs
Tri-state Activation Time (rising) SKIP#, tTSKR(2) 1
Tri-state Exit Time PWM, t3RD(PWM)(2) 100 ns
Tri-state Exit Time SKIP#, t3RD(SKIP#)(2) 50 µs
BOOTSTRAP SWITCH
Forward Voltage, VFBST IF = 10 mA 120 240 mV
Reverse Leakage, IRLEAK VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design

6.5 Typical Characteristics

TJ = 125°C, unless stated otherwise.
graph01_SLPS430.png
Figure 2. Power Loss vs Output Current
graph03_SLPS430.png
Figure 4. Safe Operating Area (SOA) – PCB Horizontal Mount (1)
graph05p2_SLPS430.png
Figure 6. Normalized Power Loss vs Frequency
graph07p2_SLPS430.png
Figure 8. Normalized Power Loss vs Output Voltage
graph09_SLPS430.png
Figure 10. Driver Current vs Frequency
graph02_SLPS430.png
Figure 3. Power Loss vs Temperature
graph04P2_SLPS430.png
Figure 5. Typical Safe Operating Area (SOA) (1)
graph06_SLPS430.png
Figure 7. Normalized Power Loss vs Input Voltage
graph08_SLPS430.png
Figure 9. Normalized Power Loss vs Output Inductance
graph10_SLPS430.png
Figure 11. Driver Current vs Temperature
  1. The Typical CSD95375Q4M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4" (W) × 3.5" (L) × 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application Information section for detailed explanation.