SLPS223F May   2010  – October 2016 CSD86350Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
      5. 6.1.5 Calculating Power Loss and SOA
        1. 6.1.5.1 Design Example
        2. 6.1.5.2 Calculating Power Loss
        3. 6.1.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q5D Tape and Reel Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DQY|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 25 V
TG to TGR –8 10
BG to PGND –8 10
Pulsed current rating, IDM(2) 120 A
Power dissipation, PD 13 W
Avalanche energy, EAS Sync FET, ID = 100 A, L = 0.1 mH 500 mJ
Control FET, ID = 58 A, L = 0.1 mH 168
Operating junction, TJ –55 150 °C
Storage temperature, TSTG –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µs, duty cycle ≤ 1%.

5.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VGS Gate drive voltage 4.5 8 V
VIN Input supply voltage 22 V
fSW Switching frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating current 40 A
TJ Operating temperature 125 °C

5.3 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(1)(2) 102 °C/W
Junction-to-ambient thermal resistance (max Cu)(1)(2) 50 °C/W
RθJC Junction-to-case thermal resistance (top of package)(2) 20 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 2 °C/W
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2 oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.4 Power Block Performance

TA = 25° (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power loss(1) VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 25 A,
fSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25°C
2.8 W
IQVIN VIN quiescent current TG to TGR = 0 V
BG to PGND = 0 V
10 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high-current 5-V driver IC.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 25 25 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 0.9 1.4 2.1 0.9 1.1 1.6 V
ZDS(on) Drain-to-source on impedance VIN = 12 V, VDD = 5 V,
VOUT = 1.3 V, IOUT = 25 A,
fSW = 500 kHz, LOUT = 0.3 µH
5 1.1
gfs Transconductance VDS = 10 V, IDS = 20 A 103 132 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance(1) VGS = 0 V, VDS = 12.5 V,
f = 1 MHz
1440 1870 3080 4000 pF
COSS Output capacitance(1) 645 840 1550 2015 pF
CRSS Reverse transfer capacitance(1) 22 29 45 59 pF
RG Series gate resistance(1) 1.4 2.8 1.4 2.8 Ω
Qg Gate charge total (4.5 V)(1) VDS = 12.5 V,
IDS = 20 A
8.2 10.7 19.4 25 nC
Qgd Gate charge – gate-to-drain 1 2.5 nC
Qgs Gate charge – gate-to-source 3.2 5.1 nC
Qg(th) Gate charge at Vth 1.9 2.8 nC
QOSS Output charge VDS = 12 V, VGS = 0 V 9.9 28 nC
td(on) Turnon delay time VDS = 12.5 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
8 9 ns
tr Rise time 21 23 ns
td(off) Turnoff delay time 9 24 ns
tf Fall time 2.3 21 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.85 1 0.77 1 V
Qrr Reverse recovery charge Vdd = 12 V, IF = 20 A,
di/dt = 300 A/μs
16 40 nC
trr Reverse recovery time 22 32 ns
(1) Specified by design.
CSD86350Q5D M0189-01_LPS223.gif
Max RθJA = 50°C/W when mounted on 1-in2 (6.45-cm2) of 2-oz (0.071-mm) thick Cu.
CSD86350Q5D M0190-01_LPS223.gif
Max RθJA = 102°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise.
CSD86350Q5D G001_LPS223.gif
Figure 1. Power Loss vs Output Current
CSD86350Q5D G003_LPS223.gif
Figure 3. Safe Operating Area – PCB Vertical Mount (1)
CSD86350Q5D G005_LPS223.gif
Figure 5. Typical Safe Operating Area (1)
(1)The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) x 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation for detailed explanation.
CSD86350Q5D G002_LPS223.gif
Figure 2. Normalized Power Loss vs Temperature
CSD86350Q5D G004_LPS223.gif
Figure 4. Safe Operating Area – PCB Horizontal Mount (1)
CSD86350Q5D G006_LPS223.gif
Figure 6. Normalized Power Loss vs Switching Frequency
CSD86350Q5D G008_LPS223.gif
Figure 8. Normalized Power Loss vs Output Voltage
CSD86350Q5D G007_LPS223.gif
Figure 7. Normalized Power Loss vs Input Voltage
CSD86350Q5D G009_LPS223.gif
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD86350Q5D G010_LPS223.gif
Figure 10. Control MOSFET Saturation
CSD86350Q5D G012_LPS223.gif
Figure 12. Control MOSFET Transfer
CSD86350Q5D G014_LPS223.gif
Figure 14. Control MOSFET Gate Charge
CSD86350Q5D G016_LPS223.gif
Figure 16. Control MOSFET Capacitance
CSD86350Q5D G018_LPS223.gif
Figure 18. Control MOSFET VGS(th)
CSD86350Q5D G020_LPS223.gif
Figure 20. Control MOSFET RDS(on) vs VGS
CSD86350Q5D G022_LPS223.gif
Figure 22. Control MOSFET Normalized RDS(on)
CSD86350Q5D G024_LPS223.gif
Figure 24. Control MOSFET Body Diode
CSD86350Q5D G026_LPS223.gif
Figure 26. Control MOSFET Unclamped Inductive Switching
CSD86350Q5D G011_LPS223.gif
Figure 11. Sync MOSFET Saturation
CSD86350Q5D G013_LPS223.gif
Figure 13. Sync MOSFET Transfer
CSD86350Q5D G015_LPS223.gif
Figure 15. Sync MOSFET Gate Charge
CSD86350Q5D G017_LPS223.gif
Figure 17. Sync MOSFET Capacitance
CSD86350Q5D G019_LPS223.gif
Figure 19. Sync MOSFET VGS(th)
CSD86350Q5D G021_LPS223.gif
Figure 21. Sync MOSFET RDS(on) vs VGS
CSD86350Q5D G023_LPS223.gif
Figure 23. Sync MOSFET Normalized RDS(on)
CSD86350Q5D G025_LPS223.gif
Figure 25. Sync MOSFET Body Diode
CSD86350Q5D G027_LPS223.gif
Figure 27. Sync MOSFET Unclamped Inductive Switching