ZHCSCO7B June   2014  – April 2017 CSD17573Q5B

PRODUCTION DATA.  

  1. 1特性
  2. 2应用范围
  3. 3说明
  4. 4修订历史记录
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6器件和文档支持
    1. 6.1 接收文档更新通知
    2. 6.2 社区资源
    3. 6.3 商标
    4. 6.4 静电放电警告
    5. 6.5 Glossary
  7. 7机械、封装和可订购信息
    1. 7.1 Q5B 封装尺寸
    2. 7.2 建议 PCB 布局
    3. 7.3 建议模板布局
    4. 7.4 Q5B 卷带信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DNK|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.1 1.4 1.8 V
RDS(on) Drain-to-source on resistance VGS = 4.5 V, ID = 35 A 1.19 1.45 mΩ
VGS = 10 V, ID = 35 A 0.84 1.00
gƒs Transconductance VDS = 15 V, ID = 35 A 181 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 6920 9000 pF
Coss Output capacitance 769 1000 pF
Crss Reverse transfer capacitance 300 390 pF
RG Series gate resistance 0.9 1.8 Ω
Qg Gate charge total (4.5 V) VDS = 15 V, ID = 35 A 49 64 nC
Qgd Gate charge gate-to-drain 11.9 nC
Qgs Gate charge gate-to-source 17.1 nC
Qg(th) Gate charge at Vth 8.6 nC
Qoss Output charge VDS = 30 V, VGS = 0 V 21 nC
td(on) Turnon delay time VDS = 15 V, VGS = 10 V,
IDS = 35 A, RG = 0 Ω		 6 ns
tr Rise time 20 ns
td(off) Turnoff delay time 40 ns
tƒ Fall Time 7 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 35 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDS= 15 V, IF = 35 A,
di/dt = 300 A/μs		 29 nC
trr Reverse recovery time 21 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 0.8 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 50 °C/W
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.

CSD17573Q5B M0137-01_LPS198.gif
Max RθJA = 50°C/W when mounted on 1 in2 (6.45 cm2) of
2-oz (0.071-mm) thick Cu.
CSD17573Q5B M0137-02_LPS198.gif
Max RθJA = 125°C/W when mounted on a minimum pad area of
2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)
CSD17573Q5B graph01_SLPS492.png
Figure 1. Transient Thermal Impedance
CSD17573Q5B graph02_SLPS492.png
Figure 2. Saturation Characteristics
CSD17573Q5B graph04_SLPS492.png
ID = 35 A VDS = 15 V
Figure 4. Gate Charge
CSD17573Q5B graph06_SLPS492.png
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD17573Q5B graph08_SLPS492.png
ID = 35 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD17573Q5B D010_SLPS492.gif
Single pulse, max RθJC = 0.8°C/W
Figure 10. Maximum Safe Operating Area
CSD17573Q5B graph12_SLPS492.png
Figure 12. Maximum Drain Current vs Temperature
CSD17573Q5B graph03_SLPS492.png
VDS = 5 V
Figure 3. Transfer Characteristics
CSD17573Q5B graph05_SLPS492.png
Figure 5. Capacitance
CSD17573Q5B graph07_SLPS492.png
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17573Q5B graph09_SLPS492.png
Figure 9. Typical Diode Forward Voltage
CSD17573Q5B graph11_SLPS492.png
Figure 11. Single Pulse Unclamped Inductive Switching