SCAS841D February   2007  – December 2016 CDCLVD110A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: LVDS
    7. 6.7 Jitter Characteristics
    8. 6.8 Control Register Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Information
      2. 8.4.2 LVDS Receiver Input Termination
      3. 8.4.3 Input Termination
      4. 8.4.4 LVDS Output Termination
      5. 8.4.5 Control Inputs Termination
    5. 8.5 Programming
      1. 8.5.1 Specification of Control Register
        1. 8.5.1.1 Programmable Mode (EN = 1)
        2. 8.5.1.2 Standard Mode (EN = 0)
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VDD –0.3 2.8 V
Input voltage, VI –0.2 VDD + 0.2 V
VI output voltage, VO –0.2 VDD + 0.2 V
Driver short-circuit current, IOSD (Qn, Qn) Continuous
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) HBM 1.5-kΩ, 100-pF

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 2.375 2.5 2.625 V
VIC Receiver common-mode input voltage 0.5 × |VID| VDD – 0.5 × |VID| V
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) CDCLVD110A UNIT
VF (LQFN) RHB (VQFN)
32 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 85.1 45.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.3 37.5 °C/W
RθJB Junction-to-board thermal resistance 49.4 17.9 °C/W
ψJT Junction-to-top characterization parameter 0.9 1.5 °C/W
ψJB Junction-to-board characterization parameter 48.7 17.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 9.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
|VOD| Differential output voltage RL = 100 Ω 250 450 600 mV
ΔVOD VOD magnitude change 50 mV
VOS Offset voltage –40°C to 85°C 0.95 1.2 1.45 V
ΔVOS VOS magnitude change 350 mV
IOS Output short-circuit current VO = 0 V –20 mA
|VOD| = 0 V 20
VBB Reference output voltage VDD = 2.5 V, IBB = –100 µA 1.15 1.25 1.35 V
CO Output capacitance VO = VDD or GND 3 pF
RECEIVER
VIDH Input threshold high 100 mV
VIDL Input threshold low –100 mV
|VID| Input differential voltage 200 mV
IIH Input current, CLK0/CLK0 VI = VDD –5 5 µA
IIL Input current, CLK1/CLK1 VI = 0 V –5 5 µA
CI Input capacitance VI = VDD or GND 3 pF
SUPPLY CURRENT
IDD Supply current,
full loaded and no load		 All outputs enabled and loaded, RL = 100 Ω, f = 100 MHz 100 110 mA
All outputs enabled and loaded, RL = 100 Ω, f = 800 MHz 150 160
Outputs enabled, no output load, f = 0 Hz 35
IDDZ Supply current, 3-state All outputs 3-state by control logic, f = 0 Hz 35 mA

6.6 Switching Characteristics: LVDS

over recommended operating free-air temperature range and VDD = 2.5 V ±5% (unless otherwise noted)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 MIN TYP MAX UNIT
tPLH Propagation delay low-to-high CLK0, CLK0 CLK1, CLK1 Qn, Qn 2 3 ns
tPHL Propagation delay high-to-low CLK0, CLK0 CLK1, CLK1 Qn, Qn 2 3 ns
tduty Duty cycle CLK0, CLK0 CLK1, CLK1 Qn, Qn 45% 55%
tsk(o) Output skew Any Qn, Qn 30 ps
tsk(p) Pulse skew Any Qn, Qn 50 ps
tsk(pp) Part-to-part skew Any Qn, Qn 600 ps
tr Output rise time, 20% to 80%,
RL = 100 Ω, CL = 5 pF		 Any Qn, Qn 350 ps
tf Output fall time, 20% to 80%,
RL = 100 Ω, CL = 5 pF		 Any Qn, Qn 350 ps
fclk Max input frequency CLK0, CLK0 CLK1, CLK1 Any Qn, Qn 900 1100 MHz

6.7 Jitter Characteristics

characterized with CDCLVD110 performance EVM, VDD = 3.3 V, outputs not under test are terminated to 50 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tjitterLVDS Additive phase jitter from input to LVDS output Q3 and Q3 12 kHz to 5 MHz, fout = 30.72 MHz 281 fs rms
12 kHz to 20 MHz, fout = 125 MHz 111

6.8 Control Register Characteristics

over recommended operating free-air temperature range, VDD = 2.5 V ±5% (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMAX Maximum frequency of shift register 100 150 MHz
tsu Set-up time, clock to SI 2 ns
th Hold time, clock to SI 1.5 ns
tremoval Removal time, enable to clock 1.5 ns
tstartup Start-up time after disable through SI 1 µs
tw Clock pulse width, minimum 3 ns
VIH Logic input high VDD = 2.5 V 2 V
VIL Logic input low VDD = 2.5 V 0.8 V
IIH Input current, CK pin VI = VDD –5 5 µA
Input current, SI and EN pins VI = VDD 10 –30
IIL Input current, CK pin VI = GND –10 30 µA
Input current, SI and EN pins VI = GND –5 5

6.9 Typical Characteristics

Input clock RMS jitter is 55.4 fs from 12 kHz to 20 MHz, additive RMS jitter is 70.4 fs, TA = 25°C, and VDD = 2.5 V (unless otherwise noted).
CDCLVD110A CDCLVD110A_PN_IN_OUT_CLK0_125M.gif Figure 1. 125-MHz Input and Output Phase Noise Plot