ZHCSD30
November 2014
CDCL1810A
PRODUCTION DATA.
1
特性
2
应用
3
说明
4
简化电路原理图
5
修订历史记录
6
Device Comparison Tables
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
Handling Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
DC Electrical Characteristics
8.6
AC Electrical Characteristics
8.7
AC Electrical Characteristics for the SDA/SCL Interface
8.8
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Output Enable/Disable
9.3.2
SDA/SCL Interface
9.3.2.1
SDA/SCL Bus Slave Device Address
9.3.2.2
SDA/SCL Connections Recommendations
9.4
Device Functional Modes
9.5
Programming
9.5.1
SDA/SCL Interface
9.5.2
Command Code Definition
9.5.3
SDA/SCL Timing Characteristics
9.5.4
SDA/SCL Programming Sequence
9.6
Register Maps
9.6.1
SDA/SCL Bus Configuration Command Bitmap
9.6.1.1
Byte 0:
9.6.1.2
Byte 1:
9.6.1.3
Byte 2:
9.6.1.4
Byte 3:
9.6.1.5
Byte 4:
9.6.1.6
Byte 5:
9.6.1.7
Byte 6:
10
Application and Implementation
10.1
Application Information
10.1.1
Clock Distribution for Multiple TI Keystone DSPs
10.1.1.1
Design Requirements
10.1.1.2
Detailed Design Procedure
10.1.1.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
器件和文档支持
13.1
商标
13.2
静电放电警告
13.3
术语表
14
机械封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGZ|48
MPQF123F
散热焊盘机械数据 (封装 | 引脚)
RGZ|48
QFND014T
订购信息
zhcsd30_oa
11 Power Supply Recommendations
The device is designed to operate from an input voltage supply of 1.8 V for analog supply (AVDD) and core supply (VDD). Both AVDD and VDD can be supplied by a single source.