SCAS844F August   2007  – October  2016 CDCE949 , CDCEL949

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 EEPROM Specification
    7. 7.7 Timing Requirements: CLK_IN
    8. 7.8 Timing Requirements: SDA/SCL
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Control Terminal Setting
      2. 9.3.2 Default Device Setting
      3. 9.3.3 SDA/SCL Serial Interface
      4. 9.3.4 Data Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 SDA/SCL Hardware Interface
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Configuration Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
    2. 13.2 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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Features

  • Member of Programmable Clock Generator Family
    • CDCEx913: 1 PLLs, 3 Outputs
    • CDCEx925: 2 PLLs, 5 Outputs
    • CDCEx937: 3 PLLs, 7 Outputs
    • CDCEx949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 8 to 32 MHz
    • On-Chip VCXO: Pull-Range ±150 ppm
    • Single-Ended LVCMOS Up to 160 MHz
  • Free Selectable Output Frequency Up to 230 MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE949: 3.3 V and 2.5 V
    • CDCEL949: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Core Supply
  • Wide Temperature Range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)

Applications

    D-TVs, STBs, IP-STBs, DVD Players, DVD Recorders, and Printers

Description

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCE949
CDCEL949
TSSOP (24) 7.80 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

CDCE949 CDCEL949 scas849_typ_app.gif

Revision History

Changes from E Revision (August 2016) to F Revision

  • Changed data sheet title from: CDCEx949 Programmable 4-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs to: CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI ReductionGo

Changes from D Revision (March 2010) to E Revision

  • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Condensed down bullets in FeaturesGo
  • Deleted 'General Purpose Frequency Synthesizing' from ApplicationsGo
  • Updated values in the Thermal Information table to align with JEDEC standards Go
  • Changed Byte Read Protocol image, second S to SrGo
  • Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4Go
  • Changed under Example, fifth row, N", 2 places TO N'Go

Changes from C Revision (October 2009) to D Revision

  • Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, PLL3, & PLL4 Configure Register TableGo

Changes from B Revision (September 2009) to C Revision

  • Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information.Go

Changes from A Revision (December 2007) to B Revision

  • Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions tableGo

Changes from * Revision (August 2007) to A Revision

  • Changed the THERMAL RESISTANCE FOR TSSOP tableGo
  • Changed Generic Configuration Register table RID From: 0h To: XbGo
  • Added note to the PWDN description, Generic Configuration Register tableGo