Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

(1) CL includes probe
and test-fixture capacitance.
Figure 6-1 Load Circuit for 3-State
Outputs

(1) The
greater between tPLH and tPHL is the same as
tpd.
Figure 6-2 Voltage Waveforms,
Standard CMOS Inputs Setup Propagation Delays
(1) The greater between
tr and tf is the same as tt.
Figure 6-4 Voltage Waveforms, Input
and Output Transition Times for Standard CMOS Input Devices
(1) tPLZ and
tPHZ are the same as tdis.
(2) tPZL and
tPZH are the same as ten.
Figure 6-3 Voltage Waveforms,
Standard CMOS Inputs Propagation Delays

(1) The greater between
tPLH and tPHL is the same as
tpd.
Figure 6-5 Voltage Waveforms,
TTL-Compatible CMOS Inputs Propagation Delays
(1) tPLZ and
tPHZ are the same as tdis.
(2) tPZL and
tPZH are the same as ten.
Figure 6-6 Voltage Waveforms,
TTL-Compatible CMOS Inputs Propagation Delays