ZHCSPR7E November   1998  – October 2022 CD54HC374 , CD54HC574 , CD54HCT374 , CD54HCT574 , CD74HC374 , CD74HC574 , CD74HCT374 , CD74HCT574

PRODUCTION DATA  

  1. 特性
  2. 说明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • J|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

Switching Characteristics

CL = 50 pF, Input tr, tf = 6 ns
PARAMETER TEST CONDITIONS VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL

Propagation delay

Clock to output

CL = 50 pF 2 165 205 250 ns
4.5 33 41 50
CL = 15 pF 5 15 ns
CL = 50 pF 6 28 35 43
tPLZ, tPHZ Output disable to Q CL = 50 pF 2 135 170 205 ns
4.5 27 34 41
CL = 15 pF 5 11 ns
CL = 50 pF 6 23 29 35
tPZL, tPZH Output enable to Q CL = 50 pF 2 150 190 225 ns
4.5 30 38 45
CL = 15 pF 5 12 ns
CL = 50 pF 6 26 33 38
fMAX Maximum clock frequency CL = 15 pF 5 60 MHz
tTHL, tTLH Output transition time CL = 50 pF 2 60 75 90 ns
4.5 12 15 18
6 10 13 15
CI Input capacitance CL = 50 pF 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1)(2) CL = 15 pF 5 39 pF
HCT TYPES
tPHL, tPLH

Propagation delay

Clock to output

CL = 50 pF 4.5 33 41 50 ns
CL = 15 pF 5 15
tPLZ, tPHZ Output disable to Q CL = 50pF 4.5 28 35 42 ns
CL = 15 pF 5 11
tPZL, tPZH Output enable to Q CL = 50 pF 4.5 30 38 45 ns
CL = 15 pF 5 12
fMAX Maximum clock frequency CL = 15 pF 5 60 MHz
tTLH, tTHL Output transition time CL = 50 pF 4.5 12 15 18 ns
CI Input capacitance CL = 50 pF 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1)(2) CL = 15 pF 5 47 pF
CPD is used to determine the dynamic power consumption, per package.
PD = CPD VCC2 fi + Σ VCC2 fO CL where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage.