ZHCS896I May   2009  – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 CC430F613x and CC430F612x Terminal Functions
      2. Table 4-2 CC430F513x Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – Low-Power Mode Supply Currents
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Thermal Resistance Characteristics, CC430F51xx
    10. 5.10 Thermal Resistance Characteristics, CC430F61xx
    11. 5.11 Digital Inputs
    12. 5.12 Digital Outputs
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 USCI (UART Mode) Clock Frequency
    28. 5.28 USCI (UART Mode)
    29. 5.29 USCI (SPI Master Mode) Clock Frequency
    30. 5.30 USCI (SPI Master Mode)
    31. 5.31 USCI (SPI Slave Mode)
    32. 5.32 USCI (I2C Mode)
    33. 5.33 LCD_B Operating Conditions
    34. 5.34 LCD_B Electrical Characteristics
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
    45. 5.45 RF1A CC1101-Based Radio Parameters
      1. 5.45.1  Recommended Operating Conditions
      2. 5.45.2  RF Crystal Oscillator, XT2
      3. 5.45.3  Current Consumption, Reduced-Power Modes
      4. 5.45.4  Current Consumption, Receive Mode
      5. 5.45.5  Current Consumption, Transmit Mode
      6. 5.45.6  Typical TX Current Consumption, 315 MHz
      7. 5.45.7  Typical TX Current Consumption, 433 MHz
      8. 5.45.8  Typical TX Current Consumption, 868 MHz
      9. 5.45.9  Typical TX Current Consumption, 915 MHz
      10. 5.45.10 RF Receive, Overall
      11. 5.45.11 RF Receive, 315 MHz
      12. 5.45.12 RF Receive, 433 MHz
      13. 5.45.13 RF Receive, 868 or 915 MHz
      14. 5.45.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
      15. 5.45.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
      16. 5.45.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
      17. 5.45.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
      18. 5.45.18 RF Transmit
      19. 5.45.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      20. 5.45.20 Typical Output Power, 315 MHz
      21. 5.45.21 Typical Output Power, 433 MHz
      22. 5.45.22 Typical Output Power, 868 MHz
      23. 5.45.23 Typical Output Power, 915 MHz
      24. 5.45.24 Frequency Synthesizer Characteristics
      25. 5.45.25 Typical RSSI_offset Values
  6. 6Detailed Description
    1. 6.1  Sub-1 GHz Radio
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Peripherals
      1. 6.10.1  Oscillator and System Clock
      2. 6.10.2  Power-Management Module (PMM)
      3. 6.10.3  Digital I/O
      4. 6.10.4  Port Mapping Controller
      5. 6.10.5  System Module (SYS)
      6. 6.10.6  DMA Controller
      7. 6.10.7  Watchdog Timer (WDT_A)
      8. 6.10.8  CRC16
      9. 6.10.9  Hardware Multiplier
      10. 6.10.10 AES128 Accelerator
      11. 6.10.11 Universal Serial Communication Interface (USCI)
      12. 6.10.12 TA0
      13. 6.10.13 TA1
      14. 6.10.14 Real-Time Clock (RTC_A)
      15. 6.10.15 Voltage Reference (REF)
      16. 6.10.16 LCD_B (Only CC430F613x and CC430F612x)
      17. 6.10.17 Comparator_B
      18. 6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
      19. 6.10.19 Embedded Emulation Module (EEM) (S Version)
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      6. 6.11.6  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      8. 6.11.8  Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      9. 6.11.9  Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptor
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuits
  8. 8器件和文档支持
    1. 8.1  入门和后续步骤
    2. 8.2  Device Nomenclature
    3. 8.3  工具和软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9机械，封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.1 特性

  • 用于低功耗无线通信应用的真正片上 系统 (SoC)
  • 宽电源电压范围：
    1.8V 至 3.6V
  • 超低功耗
    • CPU 激活模式 (AM)：160µA/MHz
    • 待机模式（LPM3 实时时钟 (RTC) 模式）：2.0µA
    • 关闭模式（LPM4 RAM 保持）：1.0µA
    • RX 中的射频：15mA，250kbps，915MHz
  • MSP430™系统和外设
    • 16 位精简指令集 (RISC) 架构、扩展内存、高达 20MHz 的系统时钟
    • 可在不到 6μs 的时间内从待机模式唤醒
    • 具有 SVS 和欠压复位功能的灵活电源管理解决方案
    • 配有的锁频环 (FLL) 的统一系统时钟
    • 配有 5 个捕捉/比较寄存器的 16 位定时器 TA0，Timer_A
    • 具有 3 个捕捉/比较寄存器的 16 位定时器 TA1，Timer_A
    • 硬件实时时钟 (RTC)
    • 两个通用串行通信接口 (USCI)
      • USCI_A0 支持 UART、IrDA 和 SPI
      • USCI_B0 支持 I2C 和 SPI
    • 具有内部基准、采样保持以及自动扫描特性的 12 位模数 转换器 (ADC) （仅限 CC430F613x 和 CC430F513x）
    • 比较器
    • 具有高达 96 段对比度控制的集成 LCD 驱动器（仅限 CC430F61xx）
    • 128 位高级加密标准 (AES) 安全加密和解密协处理器
    • 32 位硬件乘法器
    • 3 通道内部 DMA
    • 串行板上编程，无需外部编程电压
    • 内嵌式仿真模块 (EEM)
  • 高性能低于 1GHz 射频收发器内核
    • 与 CC1101 中的内核一致
    • 宽电源电压范围：2V 至 3.6V
    • 频带范围：300MHz 至 348MHz，389MHz 至 464MHz，和 779MHz 至 928MHz
    • 从 0.6 千波特率 (kbaud) 至 500 kbaud 间的可编程数据传输速率
    • 高灵敏度（0.6kBaud 时为 –117dBm，1.2kBaud 时为 –111dBm，315MHz，1% 的误包率）
    • 出色的接收器可选择性和阻断性能
    • 对于所有支持的频率，可编程输出功率高达 +12dBm
    • 支持 2-FSK、2-GFSK 和 MSK，以及 OOK 和灵活的 ASK 整形
    • 针对面向数据包系统的灵活支持：用于同步字检测、地址检查、灵活数据包长度、和自动循环冗余校验码处理的片载支持
    • 支持传输前的自动空闲信道评估 (CCA)（针对对话前监听系统）
    • 接收到的信号强度指示器 (RSSI) 数字输出
    • 适合于符合 EN 300 220（欧洲）和 FCC CFR 部分 15（美国）标准的系统
    • 适用于需要满足无线 M-Bus 标准 EN 13757‑4:2005 的系统
    • 支持异步和同步串行接收或传输模式，以向后兼容现有无线电通信协议
  • 器件比较 汇总了可用的产品系列成员