ZHCS336 数据表 | 德州仪器 TI.com.cn

ZHCS336C June 2011 – October 2016

PRODUCTION DATA.

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PAP|64
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PAP|64
- PPTD012N

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, V_MAX	BAT1⁽²⁾	–0.3	36	V
BAT voltage to any other pin	BAT to any pin	–0.3	36	V
Input voltage, V_IN	VC1, VC2, VC3, VC4, VC5, VC6	–0.3	36	V
	VC0	–0.3	2
	TS1+, TS1–, TS2+, TS2–	–0.3	6
	GPAI	–0.3	6
	GPIO	–0.3	V_REG50 + 0.3
	DRDY_N, SDO_N, FAULT_N, ALERT_N	V_BAT – 1	V_BAT + 2
	CONV_S, SDI_S, SCLK_S, CS_S	–2	1
Output voltage, V_O	CONV_N, SDI_N, SCLK_N, CS_N	–0.3	36	V
	DRDY_S, SDO_S, FAULT_S, ALERT_S	–0.3	5
	GPIO	–0.3	V_REG50 + 0.3
	CB1…CB6 (CBREF = 0x00)	–0.3	36
	REG50, AUX	–0.3	6
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	50	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to VSS of this device except where otherwise noted.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Typical values stated where T_A = 25ºC and V_BAT = 22 V, Min/Max values stated where T_A = –40˚C to 85ºC and V_BAT = 7.2 V to 27 V (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_BAT	Supply voltage	BAT	7.2		27	V
V_I	Input voltage	VCn–VC(n – 1)⁽¹⁾	1		4.5	V
		GPAI	0		2.5
		GPIO	0		V_REG50
		CBn⁽¹⁾	VC(n – 1)		VCn
		TS1+, TS1–, TS2+, TS2–	0		V_REG50/2
		Non-top IC in stack: DRDY_N, SDO_N, FAULT_N, ALERT_N		BAT + 1
		Top IC in stack: DRDY_N, SDO_N, FAULT_N, ALERT_N		BAT
		Non-bottom IC in stack: CONV_S, SDI_S, SCLK_S, CS_S		–1
		Bottom IC in stack: CONV_S, SDI_S, SCLK_S, CS_S		VSS
V_O	Output voltage	Non-bottom IC in stack: DRDY_S, SDO_S, FAULT_S, ALERT_S		1		V
		Bottom IC in stack: DRDY_S, SDO_S, FAULT_S, ALERT_S		VSS
		Non-top IC in stack: CONV_N, SDI_N, SCLK_N, CS_N		BAT – 1
		Top IC in stack: CONV_N, SDI_N, SCLK_N, CS_N		BAT
C_REG50	External capacitor	REG50 pin	2.2			µF
C_VREF	External capacitor	V_REF pin	9.2	10	15	µF
C_LDO	External capacitor	LDOx pin	2.2		3.3	µF
T_OPR	Operating temperature⁽²⁾		–40		85	°C

(1) n = 1 to 6

(2) Device specifications stated within this range.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq76PL536A	UNIT
		PAP (HTQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	24.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10	°C/W
R_θJB	Junction-to-board thermal resistance	8.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical values stated where T_A = 25°C and V_BAT = 22 V, Min/Max values stated where T_A = –40°C to 85°C and V_BAT = 7.2 V to 27 V (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
ICC_SLEEP	Supply current	No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 1		12	20	µA
ICC_PROTECT	Supply current	No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 0		45	60	µA
ICC_BALANCE	Supply current	No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, or AUX; No DC load at CBx; CB_CTRL ≠ 0; CBT_CONTROL ≠ 0; CONV_H = 0 (not converting) , IO_CTRL[SLEEP] = 0		46	60	µA
ICC_CONVERT	Supply current	No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx or CBx; CONV_S = 1 (conversion active) , IO_CTRL[SLEEP] = 0		10.5	15	mA
ICC_TSD	Supply current	Thermal shutdown activated; ALERT_STATUS[TSD] = 1		1.6		mA
REG50, INTEGRATED 5-V LDO
V_REG50	Output voltage	I_REG50OUT ≤ 0.5 mA, C = 2.2 μF to 22 μF	4.9	5	5.1	V
ΔV_REG50LINE	Line regulation	6 V ≤ BAT ≤ 27 V, I_REG50OUT = 2 mA		10	25	mV
ΔV_REG50LOAD	Load regulation	0.2 mA ≤ I_REG50OUT ≤ 2 mA			15	mV
ΔV_REG50LOAD	Load regulation	0.2 mA ≤ I_REG50OUT ≤ 5 mA			25	mV
I_REG50MAX	Current limit		12	25	35	mA
I_AUXMAX	Maximum load	AUX pin			5	mA
R_AUX	AUX output	I = 1 mA, max. capacitance = V_REG50 Capacitor: C_VAUX ≤ C_VREG50 / 10			50	Ω
LEVEL SHIFT INTERFACE
I_NTX1	North 1 transmitter current	SCLK_N, CS_N, SDI_N, CONV_N	1000	1350	1800	µA
I_NTX0	North 0 transmitter current	CS_N, CONV_N			1	µA
I_NTX0A	North 0 transmitter current	SCLK_N, SDI_N (BASE device CS_H = 1)			1	µA
I_NTX0B	North 0 transmitter current	SCLK_N, SDI_N (BASE device CS_H = 0)	50	75	110	µA
I_SRX	South 1 receiver threshold	SCLK_S, CS_S, SDI_S, CONV_S	430	550	680	µA
I_SRXH	South receiver hysteresis	SCLK_S, CS_S, SDI_S, CONV_S	50	100	200	µA
I_STX1	South 1 transmitter current	ALERT_N, FAULT_S, DRDY_S	800	1100	1400	µA
I_STX0	South 0 transmitter current	ALERT_S, FAULT_S, DRDY_S			1	µA
I_STX0B	South 0 transmitter current	SDO_S (BASE device CS_H = 0)	1	4	7	µA
I_NRX	North 1 receiver threshold	SDO_N, ALERT_N, FAULT_N, DRDY_N	420	580	720	µA
I_NRXH	North receiver hysteresis	SDO_N, ALERT_N, FAULT_N, DRDY_N	50	100	200	µA
C_IN	Input capacitance			15		pF
HOST INTERFACE
V_OH	Logic-level output voltage, high; SDO_H, FAULT_H, ALERT_H, DRDY	C_L = 20 pF, I_OH < 5 mA⁽¹⁾	4.5		V_LDOD	V
V_OL	Logic-level output voltage, low; SDO_H, FAULT_H, ALERT_H, DRDY	C_L = 20 pF, I_OL < 5 mA⁽¹⁾	VSS		0.5	V
V_IH	Logic-level input voltage, high; SCLK_H, SDI_H, CS_H, CONV		2		5.2	V
V_IL	Logic-level input voltage, low; SCLK_H, SDI_H, CS_H, CONV		VSS		0.8	V
C_IN	Input capacitance SCLK_H, SDI_H, CS_H, CONV			5		pF
I_LKG	Input leakage current SCLK_H, SDI_H, CS_H, CONV				1	µA
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
V_IH	Logic-level input voltage, high	Vin ≤ V_REG50	2			V
V_IL	Logic-level input voltage, low				0.8	V
V_OH	Output high-voltage pullup voltage	Supplied by external approximately100-kΩ resistor			V_REG50	V
V_OL	Logic-level output voltage, low	I_OL = 1 mA	0.3			V
C_IN	Input capacitance(1)			5		pF
I_LKG	Input leakage current				1	µA
CELL BALANCING CONTROL OUTPUT (CBx)
CB_z	Output impedance	1 V < V_CELL < 5 V	80	100	120	kΩ
V_RANGE	Output V		V_Cn-1		V_Cn	V
ADC COMMON SPECIFICATIONS
t_{CONV_START}	CONV high to conversion start⁽²⁾ ⁽³⁾	ADC_CONTROL[ADC_ON] = 1	5.4	6	6.6	µs
t_{CONV_START}	CONV high to conversion start⁽²⁾ ⁽³⁾	ADC_CONTROL[ADC_ON] = 0		500		µs
t_CONV	Conversion time per selected channel⁽⁴⁾	ADC_CONTROL[ADC_ON] = 1	5.4	6	6.6	µs
I_LKG	Input leakage current	Not converting		<10	100	nA
VCn (CELL) INPUTS
V_IN	Input voltage range⁽⁵⁾	VCn – VCn–1, where n = 1 to 6	0		6	V
V_RES	Voltage resolution⁽⁶⁾	14 bits		~378		µV
V_ACC	Voltage accuracy, total error, V_IN = VCn to VCn–1	–10°C ≤ T_A ≤ 50°C, 1.2 V < V_IN < 4.5 V	–5	±1	5	mV
V_ACC	Voltage accuracy, total error, V_IN = VCn to VCn–1	–40°C ≤ T_A ≤ 85°C, 1.2 V < V_IN < 4.5 V	–8		8	mV
R_IN	Effective input resistance	Converting		2		MΩ
C_IN	Input capacitance	Converting		1		pF
E_N	Noise	V_IN = 3 V			250	µV_RMS
V_BAT (V_BRICK) MEASUREMENT
V_IN	Input voltage range⁽⁵⁾, BATn to VSS	FUNCTION_CONFIG = 0101xx00b	0		30	V
V_RES	Voltage resolution⁽⁶⁾	14 bits		~1.831		mV
V_ACC	Voltage accuracy	Total error	–80	–30	20	mV
C_IN	Input capacitance	Converting		1		pF
R_IN	Effective input resistance	Converting		50		kΩ
E_N	Noise				1.5	mV_RMS
GPAI MEASUREMENT
V_IN	Input voltage range,⁽⁵⁾ GPAI+ to GPAI–		0		2.5	V
V_RES	Voltage resolution⁽⁶⁾	14 bits		~153		µV
V_ACC	Voltage accuracy, V_IN = GPAI+ – GPAI–	0.25 V ≤ V_IN ≤ 2.5 V	–7		7	mV
V_ACC	Voltage accuracy, V_IN = GPAI+ – GPAI–	V_IN = 1.25 V, T_A = 25°C		±2		mV
C_IN	Input capacitance	Converting		40		pF
R_IN	Effective input resistance	Converting		50		KΩ
E_N	Noise				150	µV_RMS
TSn MEASUREMENT
V_RES	Voltage resolution,⁽⁶⁾	14 bits, REG50 = 5 V, (Resolution ≈ V_REG50 / 2¹⁵)		~153		µV
V_ACC	Ratio accuracy, % of input⁽⁶⁾	0.25 V ≤ V_IN ≤ 2.4 V	–0.7%	±0.2%	0.7%
C_IN	Input capacitance	Converting		40		pF
R_IN	Effective input resistance	Converting		50		kΩ
E_N	Noise				150	µV_RMS
THERMAL SHUTDOWN
T_SD	Shutdown threshold	V_BAT = 20 V	125	142	156	°C
T_HYS	Recovery hysteresis			8	25	°C
UNDERVOLTAGE LOCKOUT (UVLO) and POWER-ON RESET (POR)
V_UVLO	Negative-going threshold		5		5.6	V
V_{UVLO_HSY}	Hysteresis		250	375	500	mV
UVLO_DELAY	Delay to locked-out condition	V ≤ V_UVLO MIN		15		µs
V_POR	Negative-going threshold		4		5	V
V_{POR_HSY}	Hysteresis		250	500	750	mV
POR_DELAY	Delay to disabled condition	V ≤ V_POR MIN		15		µs
t_RST	Reset delay time	V ≥ V_POR + V_{POR_HSY}	40	56	70	ms
V_{DELTA_RISE}	Voltage delta between trip points	V_UVLO – V_POR (V_BAT rising)	0.3	0.4	0.7	V
V_{DELTA_FALL}	Voltage delta between trip points	V_UVLO – V_POR (V_BAT falling)	0.4	0.52	0.7	V
BATTERY PROTECTION THRESHOLDS
V_OVR	OV detection threshold range⁽⁷⁾		2		5	V
ΔV_OVS	OV detection threshold program step			50		mV
V_OVH	OV detection hysteresis			50		mV
V_OVA1	OV detection threshold accuracy	3.3 ≤ V_{OV_SET} ≤ 4.5	–50	0	50	mV
V_OVA2	OV detection threshold accuracy	V_{OV_SET} < 3.3 or V_{OV_SET} > 4.5	–70	0	70	mV
V_UVR	UV detection threshold range⁽⁷⁾		700		3300	mV
ΔV_UVS	UV detection threshold program step			100		mV
V_UVH	UV detection hysteresis			100		mV
V_UVA	UV detection threshold accuracy		–100	0	100	mV
V_OTR	OT detection threshold range⁽⁸⁾	V_REG50 = 5 V	1		2	V
Δ_VOTS	OT detection threshold program step⁽⁸⁾			See ⁽⁹⁾		V
V_OTA	OT detection threshold accuracy⁽⁸⁾	T = 40°C to 90°C		0.04	0.05	V
ΔV_OTH	OT reset hysteresis	T = 40°C to 90°C	8%	12%	15%
BATTERY PROTECTION DELAY TIMES
t_OV	OV detection delay-time range		0		3200	ms
Δt_OV	OV detection delay-time step	COVT [µs] = 0		100		µs
Δt_OV	OV detection delay-time step	COVT [ms] = 1		100		ms
t_UV	UV detection delay-time range		0		3200	ms
Δt_UV	UV detection delay-time step	CUVT[7] (µs) = 0		100		µs
Δt_UV	UV detection delay-time step	CUVT[7] (ms) = 1		100		ms
t_OT	OT detection delay-time range		0		2550	ms
Δt_OT	OT detection delay-time step			10		ms
t_acr	OV, UV, and OT detection delay-time accuracy⁽¹⁰⁾	CUVT, (COVT) ≥ 500 µs	–12%	0%	10%
t_(DETECT)	Protection comparator detection time	V_OT or V_OV or V_UV threshold exceeded by 10 mV			100	µs
OTP EPROM PROGRAMMING CHARACTERISTICS
V_PROG	Programming voltage	V_BAT ≥ 20 V	6.75	7	7.25	V
t_PROG	Programming time	V_BAT ≥ 20 V	⁽¹¹⁾		50	ms
I_PROG	Programming current	V_BAT ≥ 20 V		10	20	mA

(1) Total simultaneous current drawn from all pins is limited by LDOD current to ≤10 mA.

(2) If ADC_CONTROL[ADC_ON] = 0, add 500 µs to conversion time to allow ADC subsystem to stabilize. This is self-timed by the part.

(3) Additional 50 ms (POR) is required before first conversion after a) initial cell connection; or b) V_BAT falls below V_POR.

(4) Plus t_{CONV_START},that is, if device is programmed for six channel conversions, total time is approximately 6 × 6 + 6 = 42 µs.

(5) 0 V may not lie within the range of measured values due to offset voltage limit and device calibration.

(6) See text for specific conversion formula.

(7) COV and CUV thresholds must be set such that COV – CUV ≥ 300 mV.

(8) Using recommended components. Consult Table 2 in text for voltage levels used.

(9) See Table 2 for trip points.

(10) Under double or multiple fault conditions (of a single type), the second or greater fault may have its delay time shortened by up to the step time for the fault. For example, the second and subsequent COV faults occurring within the delay time period for the first fault may have their delay time shortened by up to 100 µs.

(11) The write pulse is self-timed internally. V_PROG should be applied for this time at a minimum.

6.6 Timing Characteristics – AC SPI Data Interface

Typical values stated where T_A = 25°C and V_BAT = 22 V, Min/Max values stated where T_A = –40˚C to 85°C and V_BAT = 7.2 V to 27 V (unless otherwise noted), see Figure 1.

PARAMETER		TEST CONDITION	MIN	NOM	MAX	UNIT
f_SCLK	SCLK frequency⁽¹⁾		10	250	1000	kHz
SCLK_DC	SCLK_H duty cycle, t_(HIGH) / t_(SCLK) or t_(LOW) / t_(SCLK)		40%		60%
t_CS,LEAD	CS_H lead time, CS_H low to clock		50	SCLK/2		ns
t_CS,LAG	CS_H lag time. Last clock to CS_H high		10	SCLK/2		ns
t_CS,DLY	CS_H high to CS_H low (inter-packet delay requirement)		3			µs
t_ACC	CS_H access time⁽²⁾: CS_H low to SDO_H data out			125	250	ns
t_DIS	CS_H disable time⁽²⁾: CS_H high to SDO_H high impedance			2.5	2.7	µs
t_SU,SDI	SDI_H input-data setup time		15			ns
t_HD,SDI	SDI_H input-data hold time		10			ns
t_VALID,SDO	SDO_H output-data valid time SCLK_H edge to SDO_H valid	C_L ≤ 20 pF		75	110	ns

(1) Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, and so forth. See text for details.

(2) Time listed is for single device.

6.7 Vertical Communications Bus

Typical values stated where T_A = 25ºC and V_BAT = 20 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP⁽¹⁾	UNIT
t_{HV_SCLK}	Propagation delay, SCLK_H to SCLK_N	HOST = 0	40	ns
t_{VB_SCLK}	Propagation delay, SCLK_S to SCLK_N	HOST = 1	30	ns
t_{HV_CS}	Propagation delay, CS_H to CS_N	HOST = 0	40	ns
t_{VB_CS}	Propagation delay, CS_S to CS_N	HOST = 1	30	ns
t_{HV_SDI}	Propagation delay, SDI_H to SDI_N	HOST = 0	40	ns
t_{VB_SDI}	Propagation delay, SDI_S to SDI_N	HOST = 1	30	ns
t_{HV_CONV}	Propagation delay, CONV_H to CONV_N	HOST = 0	100	ns
t_{VB_CONV}	Propagation delay, CONV_S to CONV_N	HOST = 1	30	ns
t_{HV_SDO}	Propagation delay, SDO_N to SDO_H	HOST = 0	10	ns
t_{VB_SDO}	Propagation delay, SDO_N to SDO_S	HOST = 1	40	ns
t_{HV_DRDY}	Propagation delay, DRDY_N to DRDY_H	HOST = 0	60	ns
t_{VB_DRDY}	Propagation delay, DRDY_N to DRDY_S	HOST = 1	40	ns
t_{HV_FAULT}	Propagation delay, FAULT_N to FAULT_H	HOST = 0	55	ns
t_{VB_FAULT}	Propagation delay, FAULT_N to FAULT_S	HOST = 1	30	ns
t_{HV_ALERT}	Propagation delay, ALERT_N to ALERT_H	HOST = 0	65	ns
t_{VB_ALERT}	Propagation delay, ALERT_N to ALERT_S	HOST = 1	30	ns

(1) Typical values are quoted in place of MIN/MAX for design guidance only. Actual propagation delay depends heavily on wiring and capacitance in the signal path. These parameters are not tested in production due to these dependencies on system design considerations.