ZHCSCS0C September   2014  – March 2017

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Dynamic Rectifier Control
      2. 8.3.2  Dynamic Power Scaling
      3. 8.3.3  VO_REG Calculations
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Adapter Enable Functionality
      6. 8.3.6  Turning Off the Transmitter
        1. 8.3.6.1 WPC v1.2 EPT
      7. 8.3.7  Communication Current Limit
      8. 8.3.8  PD_DET and TMEM
      9. 8.3.9  TS/CTRL
      10. 8.3.10 PMODE Pin
      11. 8.3.11 I2C Communication
      12. 8.3.12 Input Overvoltage
      13. 8.3.13 Alignment Aid Using Frequency Information
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1  Wireless Power Supply Current Register 1
      2. 8.5.2  Wireless Power Supply Current Register 2
      3. 8.5.3  Wireless Power Supply Current Register 3
      4. 8.5.4  I2C Mailbox Register
      5. 8.5.5  I2C Mailbox Register 2
      6. 8.5.6  I2C Mailbox Register 3
      7. 8.5.7  Wireless Power Supply FOD RAM
      8. 8.5.8  Wireless Power User Header RAM
      9. 8.5.9  Wireless Power USER VRECT Status RAM
      10. 8.5.10 Wireless Power VOUT Status RAM
      11. 8.5.11 Wireless Power Proprietary Mode REC PWR MSByte Status RAM
      12. 8.5.12 Wireless Power REC PWR LSByte Status RAM
      13. 8.5.13 Wireless Power Prop Packet Payload RAM Byte 0
      14. 8.5.14 Wireless Power Prop Packet Payload RAM Byte 1
      15. 8.5.15 Wireless Power Prop Packet Payload RAM Byte 2
      16. 8.5.16 Wireless Power Prop Packet Payload RAM Byte 3
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 WPC v1.2 Power Supply 7-V Output With 1.4-A Maximum Current With I2C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Set Point
          2. 9.2.1.2.2 Output and Rectifier Capacitors
          3. 9.2.1.2.3 TMEM
          4. 9.2.1.2.4 Maximum Output Current Set Point
          5. 9.2.1.2.5 I2C
          6. 9.2.1.2.6 Communication Current Limit
          7. 9.2.1.2.7 Receiver Coil
          8. 9.2.1.2.8 Series and Parallel Resonant Capacitors
          9. 9.2.1.2.9 Communication, Boot, and Clamp Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Standalone 10-V WPC v1.2 Power Supply With 1-A Maximum Output Current in System Board
      3. 9.2.3 Standalone 10-V Power Supply With 1-A Maximum Output Current for 2S Charging System
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1  Output Voltage Set Point
          2. 9.2.3.2.2  Output and Rectifier Capacitors
          3. 9.2.3.2.3  TMEM
          4. 9.2.3.2.4  Maximum Output Current Set Point
          5. 9.2.3.2.5  I2C
          6. 9.2.3.2.6  Communication Current Limit
          7. 9.2.3.2.7  Receiver Coil
          8. 9.2.3.2.8  Series Resonant Capacitors
            1. 9.2.3.2.8.1 Tuning Procedure
          9. 9.2.3.2.9  Communication, Boot, and Clamp Capacitors
          10. 9.2.3.2.10 VRECT Clamp
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

YFP Package
42-Pin DSBGA
Top View
bq51025 bq51025_pinout.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AC1 B1 I AC input power from receiver resonant tank
B2
B3
AC2 B4 I
B5
B6
AD E2 I Adapter sense pin
AD-EN E3 O Push-pull driver for dual PFET circuit that can pass AD input to the OUT pin; used for adapter MUX control
BOOT1 C1 O Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier
BOOT2 C6 O
CLAMP1 E1 O Open-drain FETs used to clamp the secondary voltage by providing low impedance across secondary
CLAMP2 E6 O
COMM1 F1 O Open-drain FETs used to communicate with primary by varying reflected impedance
COMM2 F6 O
CM_ILIM G3 I Enables communication current limit when pulled low or left floating.
FOD F2 I Input that is used for scaling the received power message
ILIM G2 I/O Output current or overcurrent level programming pin
OUT D1 O Output pin, used to deliver power to the load
D2
D3
D4
D5
D6
PD_DET G6 O Open-drain output that allows user to sense when receiver is on transmitter
PGND A1 — Power and logic ground
A2
A3
A4
A5
A6
RECT C2 O Filter capacitor for the internal synchronous rectifier
C3
C4
C5
SCL E4 I SCL and SDA are used for I2C communication. Connect to ground if not needed.
SDA F4 I/O
PMODE F3 O Indicates receiver mode of operation: Low = Proprietary 10-W mode, High = Low-power mode. Gate drive output for external current limit switch. Connect 5-MΩ resistor to ground. Leave floating if unused.
TMEM G5 O TMEM allows the capacitor to be connected to GND so energy from transmitter ping can be stored to retain memory of state.
TS/CTRL G4 I Temperature sense. Can be pulled high to send end power transfer (EPT) – charge complete to TX. Can be pulled low to send EPT – over temperature
VO_REG G1 I Sets the regulation voltage for output. Default value is 0.5 V.
VIREG E5 I Rectifier voltage feedback
WPG F5 O Open-drain output that allows user to sense when power is transferred to load