6 Specifications
6.1 Absolute Maximum Ratings(1)
TA = 25°C (unless otherwise noted)
|
MIN |
MAX |
UNIT |
|
VIN to PGND |
–0.3 |
30 |
V |
|
VSW to PGND , VIN to VSW |
–0.3 |
30 |
V |
|
VSW to PGND, VIN to VSW (<10 ns) |
–7 |
33 |
V |
|
VDD to PGND |
–0.3 |
6 |
V |
|
PWM |
–0.3 |
6 |
V |
|
BOOT to PGND |
–0.3 |
35 |
V |
|
BOOT to PGND (<10 ns) |
–2 |
38 |
V |
|
BOOT to BOOT_R |
–0.3 |
6 |
V |
|
BOOT to BOOT_R (duty cycle <0.2%) |
|
8 |
V |
PD |
Power dissipation |
|
8 |
W |
TJ |
Operating temperature |
–40 |
150 |
°C |
Tstg |
Storage temperature |
–55 |
150 |
°C |
(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human body model (HBM)(1) |
±2000 |
V |
Charged device model (CDM)(2) |
±500 |
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
|
MIN |
MAX |
UNIT |
VDD |
Gate drive voltage |
4.5 |
5.5 |
V |
VIN |
Input supply voltage(1) |
|
24 |
V |
ISW |
Continuous VSW current |
VIN = 10 V, VDD = 5 V, Duty cycle = 50%, ƒSW = 130 kHz, LSW = 6 µH(2) |
|
10 |
A |
ISW-PK |
Peak VSW current(3) |
|
15 |
A |
ƒSW |
Switching frequency |
CBOOT = 0.1 µF (min) |
|
600 |
kHz |
|
On time duty cycle |
|
85% |
|
|
Minimum PWM on time |
40 |
|
ns |
|
Operating temperature |
–40 |
125 |
°C |
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 2. Peak VSW Current is applied for tp = 10 ms, duty cycle ≤ 1%
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC |
MIN |
TYP |
MAX |
UNIT |
RθJC |
Junction-to-case (top of package) thermal resistance(1) |
|
|
22.8 |
°C/W |
RθJB |
Junction-to-board thermal resistance(2) |
|
|
2.5 |
(1) RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch (1.52 mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1mm of the package.
6.5 Electrical Characteristics
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
PLOSS |
Power loss(1) |
|
VIN = 10 V, VDD = 5 V, ISW = 5 A, ƒSW = 130 kHz, LSW = 6 µH , TJ = 25°C, Duty Cycle = 50% |
|
0.53 |
|
W |
Power loss(1) |
|
VIN = 10 V, VDD = 5 V, ISW = 5 A, ƒSW = 130 kHz, LSW = 6 µH , TJ = 125°C, Duty Cycle = 50% |
|
0.68 |
|
W |
VIN |
IQ |
VIN quiescent current |
PWM = Floating, VDD = 5 V, VIN= 24 V |
|
|
1 |
µA |
VDD |
IDD |
Standby supply current |
PWM = Float |
|
130 |
|
µA |
IDD |
Operating supply current |
PWM = 50% Duty cycle, ƒSW = 130 kHz |
|
2 |
|
mA |
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT |
VDD Rising |
Power-on reset |
|
|
|
4.15 |
V |
VDD Falling |
UVLO |
|
3.7 |
|
|
V |
|
Hysteresis |
|
|
0.2 |
|
V |
PWM I/O SPECIFICATIONS |
RI |
Input impedance |
Pull up to VDD |
|
1700 |
|
kΩ |
Pull down (to GND) |
|
800 |
|
VIH |
Logic level high |
|
2.65 |
|
|
V |
VIL |
Logic level low |
|
|
|
0.6 |
VIH |
Hysteresis |
|
|
0.2 |
|
VTS |
Tri-state voltage |
|
1.3 |
|
2 |
tTHOLD(off1) |
Tri-state activation time (falling) PWM |
|
|
60 |
|
ns |
tTHOLD(off2) |
Tri-state activation time (rising) PWM |
|
|
60 |
|
t3RD(PWM) |
Tri-state exit time PWM (1) |
|
|
|
100 |
ns |
BOOTSTRAP SWITCH |
VFBST |
Forward voltage |
IF = 10 mA |
|
120 |
240 |
mV |
IRLEAK |
Reverse leakage(1) |
VBOOT – VDD = 25 V |
|
|
2 |
µA |
(1) Specified by design