SLUS900F December   2008  – August 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings #GUID-4430518C-46E5-4467-8224-12E6F82A6B20/AMR001
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 IRQ Function
      2. 6.3.2 VBACK Switchover
      3. 6.3.3 Trickle Charge
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
  8. 7 Register Maps
    1. 7.1 I2C Read After Backup Mode
    2. 7.2 Normal Register Descriptions
      1. 7.2.1  SECONDS Register (address = 0x00) [reset = 0XXXXXXb]
      2. 7.2.2  MINUTES Register (address = 0x01) [reset = 1XXXXXXb]
      3. 7.2.3  CENT_HOURS Register (address = 0x02) [reset = XXXXXXXXb]
      4. 7.2.4  DAY Register (address = 0x03) [reset = 00000XXXb]
      5. 7.2.5  DATE Register (address = 0x04) [reset = 00XXXXXXb]
      6. 7.2.6  MONTH Register (address = 0x05) [reset = 000XXXXXb]
      7. 7.2.7  YEARS Register (address = 0x06) [reset = XXXXXXXXb]
      8. 7.2.8  CAL_CFG1 Register (address = 0x07) [reset = 10000000b]
      9. 7.2.9  TCH2 Register (address = 0x08) [reset = 10010000b]
      10. 7.2.10 CFG2 Register (address = 0x09) [reset = 10101010b]
    3. 7.3 Special Function Registers
      1. 7.3.1 SF KEY 1 Register (address = 0x20) [reset = 00000000b]
      2. 7.3.2 SF KEY 2 Register (address = 0x21) [reset = 00000000b]
      3. 7.3.3 SFR Register (address = 0x22) [reset = 00000000b]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reading From a Register
        2. 8.2.2.2 Leap Year Compensation
        3. 8.2.2.3 Utilizing the Backup Supply
        4. 8.2.2.4 Calibration Example of Crystal Input
        5. 8.2.2.5 Calculating the Super Capacitor Values Example
      3. 8.2.3 Application Curves
    3.     Power Supply Recommendations
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Community Resources
    3. 9.3 Trademarks
  11. 10Revision History
  12.   Mechanical, Packaging, and Orderable Information

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8.3.1 Layout Guidelines

The VCC pin must be bypassed to GND using a low-ESR ceramic bypass capacitor with a minimum recommended value of 1µF. This capacitor must be placed as close to the VCC and GND pins as possible with thick trace or ground plane connection to the device GND pin.

Locate the 32.768kHz crystal oscillator as close as possible to the OSCI and OSCO pins. This minimizes stray capacitance.