7.4.1 High Impedance Mode

High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq24266. During Hi-Z mode, the buck converter is off, and the battery FET and BGATE are on. SYS is powered by BAT. The bq24266 is in Hi-Z mode when V_IN < V_UVLO or the IUSB1, IUSB2, and IUSB3 pins are all driven high. Hi-Z mode resets the safety timer. When exiting Hi-Z mode, charging resumes in approximately 110ms.

7.4.2 Battery Only Connected

When the battery is connected with no input source, the battery FET is turned on.  After the battery rises above V_BATUVLO and the deglitch time, t_DGL(BAT), the SYS output starts to rise.  In this mode, the current is not regulated; however, there is a short circuit current limit.  If the short circuit limit (I_LIM(DISCHG)) is reached for the deglitch time (t_DGL(SC)), the battery FET is turned off for the recovery  time (t_REC(SC)).  After the recovery time, the battery FET is turned on to test and see if the short has been removed.  If it has not, the FET turns off and the process repeats until the short is removed.  This process protects the internal FET from over current.  If an external FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the battery and t_DGL(BAT) is not applicable. 

7.4.3 Input Connected

7.4.3.1 Input Voltage Protection in Charge Mode

7.4.3.1.1 Sleep Mode

The bq24266 enters the low-power sleep mode if the voltage on V_IN falls below sleep-mode entry threshold, V_BAT+V_SLP, and V_IN is higher than the undervoltage lockout threshold, V_UVLO. In sleep mode, the input is isolated from the battery. This feature prevents draining the battery during the absence of V_IN. When V_IN < V_BAT+ V_SLP, the bq24266 turns off the PWM converter and turns the battery FET and BGATE on. Once V_IN > V_BAT+ V_SLP, the device initiates a new charge cycle.

7.4.3.1.2 Input Voltage Based Dynamic Power Management (V_IN-DPM)

During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage deceases. Also, at higher currents, large input line impedances may cause the voltage at the device to droop. Once the supply drops to V_{IN_DPM} (default 4.2V), the charge current limit is reduced to prevent the further drop of the supply. When the IC enters this mode, the charge current is lower than the set value. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change. Figure 9 shows the V_IN-DPM behavior to a current limited source. In this figure the input source has a 2A current limit and the device is charging at 1A. A 2.5A load transient then occurs on V_SYS causing the adapter to hit its current limit and collapse, while V_SYS goes from V_SYSREG(LO) to V_MINSYS. The safety timer is extended while V_IN-DPM is active. Additionally, termination is disabled.

The V_INDPM threshold for the adapter modes (1.5A and 2.5A) is set using a resistor divider with VDPM connected to the center tap. Select 10kΩ for the bottom resistor. The top resistor is selected using equation Equation 1.

Where V_{IN_DPM} is the desired V_{IN_DPM} threshold and VDPM is the regulation threshold at the pin specified in the Electrical Characteristics table.

Equation 1.

.

Figure 9. bq24266 V_IN-DPM

7.4.3.1.3 Input Overvoltage Protection

The built-in input overvoltage protection protects the bq24266 and downstream components connected to SYS and/or BAT against damage from overvoltage on the input supply (Voltage from V_IN to PGND). When V_IN > V_OVP, the bq24266 turns off the PWM converter immediately. After the deglitch time t_{DGL(BUCK_OVP)}, an OVP fault is determined to exist. During the OVP fault the bq24266 turns the battery FET and BGATE on. Once the OVP fault is removed, the device returns to normal operation.

The OVP threshold is 14V for operation from standard adapters and from 12V sources.

7.4.3.2 Charge Profile

When a valid input source is connected (V_IN>V_UVLO and V_BAT+V_SLP<V_IN<V_OVP), charging is enabled.

The charge current, I_CHARGE, is set using the ISET pin by connecting a resistor form ISET to GND. The current is programmable from 500mA to 3A using Equation 2, where I_CHARGE is in Amperes, and K_ISET is the value specified in the Electrical Characteristics table.

Equation 2.

The bq24266 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Charging is done through the internal battery MOSFET. There are 6 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop (MINSYS), input current limit and V_IN-DPM. During the charging process, all six loops are enabled and the one that is dominant takes control. The minimum system output feature regulates the system voltage to V_SYSREG(LO), so that startup is enabled even for a missing or deeply discharged battery. Figure 10 shows a typical charge profile including the minimum system output voltage feature.

7.4.4 Battery Charging Process

When the battery is deeply discharged or shorted, the bq24266 applies a I_BATSHRT current to close the battery protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is off and the system output is regulated to V_SYSREG(LO). Once the battery rises above V_BATSHRT, the charge current is regulated to the value set by ISET. The battery FET is linearly regulated to maintain the system voltage at V_SYSREG(LO). Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for very long. If the die temperature does heat up, the thermal regulation loop reduces the input current to maintain a die temperature at 125°C. If the current limit for the SYS output is reached (limited by the input current limit, V_IN-DPM, or 100% duty cycle), the SYS output drops to the V_MINSYS output voltage. When this happens, the charge current is reduced to ensure the system is supplied with all the current that is needed while maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode (see the “Dynamic Power Path Management” section for more details).

Once the battery is charged enough that the system voltage rises above V_SYSREG(LO) (approximately 3.5V), the battery FET is turned on fully and the battery is charged with the full programmed charge current set by ISET. The charge current is regulated to I_CHARGE until the voltage between BAT and PGND reaches the regulation voltage. The voltage between BAT and PGND is regulated to V_BATREG (CV mode) while the charge current naturally tapers down as shown in Figure 10. During CV mode, the SYS output remains connected to the battery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below ~350mA to provide increased accuracy during termination. This will show a small rise in the SYS voltage when the R_DS(ON) increases below ~350mA.

Once the charge current tapers down to the termination threshold, I_TERM, and the battery voltage is above the recharge threshold, the bq24266 terminates charge, turns off the battery charging FET and enters battery detection (see Battery Detection section for more details). The system output is regulated to the V_SYSREG(HI) and supports the full current available from the input. The battery supplement mode is available to supply any SYS load that cannot be supported by the input source (see the Dynamic Power Path Management section for more details). The termination current level is set to 10% of the charge current. Termination is disabled when any loop is active other than CC or CV. This includes V_INDPM, input current limit, or thermal regulation. Termination is also disabled during TS warm/cool conditions.

A charge cycle is initiated when one of the following conditions is detected:

1. The battery voltage falls below the V_BATREG-V_RCH threshold.
2. IN Power-on reset (POR)
3. Charge disabled then enabled using CE
4. IUSB toggeld from high impedance to any charge state

7.4.5 Charge Time Optimizer

The CC to CV transition is enhanced in the bq24266 architecture. The "knee" between CC and CV is very sharp. This enables the charger to remain in CC mode as long as possible before beginning to taper the charge current (CV mode). This provides a decrease in charge time as compared to older topologies.

7.4.6 Battery Detection

When termination conditions are met, a battery detection cycle is started.  During battery detection, I_DETECT is pulled from V_BAT for t_DETECT(SNK) to verify there is a battery. If the battery voltage remains above V_DETECT for the full duration of t_DETECT(SNK), a battery is determined to present and the IC enters “Charge Done”. If V_BAT falls below V_DETECT, battery detection continues. The next cycle of battery detection, the bq24266 turns on I_BATSHRT for t_DETECT(SRC). If V_BAT rises to V_DET(SRC1), the current source is turned off. In order to keep VBAT high enough to close the battery protector, the current source turns on if V_BAT falls to V_DET(SRC2). The source cycle continues for t_DETECT(SRC). After t_DETECT(SRC), the battery detection continues through another current sink cycle. Battery detection continues until charge is disabled, the bq24266 enters high-z mode or a battery is detected. Once a battery is detected, a new charge cycle begins. With no battery connected, the BAT output will transition from V_RCH to PGND with a high period of t_DETECT(SRC) and a low period of t_DETECT(SNK). See Figure 16 in the Application Curves section.

7.4.7 Battery Overvoltage Protection (BOVP)

If the battery is ever above the battery OVP threshold (V_BOVP), the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to safe operating levels. In this condition, the V_BATREG is reset and may be below the battery voltage. This state can be entered when TS WARM conditions decrease the V_BATREG to less than the battery voltage. The battery OVP condition is cleared when the battery voltage falls below the hysteresis of V_BOVP by the battery discharging. When a battery OVP event exists for t_DGL(BOVP), the bq24266 turns the battery FET and BGATE on.

7.4.8 Dynamic Power Path Management

The bq24266 features a SYS output that powers the external system load connected to the battery. This output is active whenever a valid source is connected to IN or BAT. When V_SYS > V_SYSREG(LO), the SYS output is connected to V_BAT. If the battery voltage falls to V_MINSYS, V_SYS is regulated to the V_SYSREG(LO) threshold to maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current into the battery. The current from the supply is shared between charging the battery and powering the system load at SYS. The dynamic power path management (DPPM) circuitry of the bq24266 monitors the current limits continuously and if the SYS voltage falls to the V_MINSYS threshold, it adjusts charge current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load increases further, the bq24266 enters battery supplement mode. During supplement mode, the battery FET is turned on and V_BAT = V_SYS while the battery supplements the system load.

Figure 11. Example DPPM Response (V_Supply = 5V, V_BAT = 3.1V, 1.5A Input Current Limit)

7.4.9 Battery Discharge FET (BGATE)

The bq24266 contains a MOSFET driver to drive an external discharge FET between the battery and the system output. This external FET provides a low impedance path for supplying the system from the battery. Connect BGATE to the gate of the external discharge P-channel MOSFET. BGATE is on (low) under the following conditions:

1. No input supply connected.
2. IUSB1, IUSB2, IUSB3 pins = high

7.4.10 IUSB1, IUSB2, and IUSB3 Input

The bq24266 has three inputs that configure the input current limit and VINDPM thresholds. These input are also used to enable the USB OTG Boost function. The bq24266 incorporates all of the necessary input current limits to support USB2.0 and USB3.0 standards, as well as 1.5A to support wall adapters. Driving IUSB1, IUSB2, and IUSB3 all high places the bq24266 in Hi-Z mode where the buck converter is shutdown regardless if an input is connected to IN. Table 1 shows the configuration for IUSB1, IUSB2, and IUSB3.

7.4.11 Safety Timer in Charge Mode

At the beginning of the charging process, the bq24266 starts the safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode where charging is disabled. CE, or power must be toggled in order to clear the safety timer fault. The bq24266 also contains a 2X_TIMER that doubles the safety timer to prevent premature safety timer expiration when the charge current is reduced by a load on SYS or a NTC condition. When 2X_TIMER is active, the timer runs at half speed when any loop is active other than CC or CV. This includes V_INDPM, input current limit, or thermal regulation. The timer also runs at half speed during TS warm/cool conditions.

7.4.12 LDO Output (DRV)

The bq24266 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other circuitry. Additionally, DRV supplies up to 10mA external loads to power the PG or CHG LED or the USB transceiver circuitry. The maximum value of the DRV output is 5.3V so it ideal to protect voltage sensitive USB circuits. The LDO is on whenever a supply is connected to the input of the bq24266. The DRV is disabled under the following conditions:

1. V_SUPPLY < UVLO
2. V_SUPPLY < V_BAT + V_SLP
3. Thermal Shutdown

7.4.13 External NTC Monitoring (TS)

The bq24266 provides a flexible, voltage based TS input for monitoring the battery pack NTC thermistor. The bq24266 implements the full JEITA standard. The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The JEITA specification is shown in Figure 12.

Figure 12. Charge Current During TS Conditions

To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (T_NTC < 0°C), the cool battery threshold (0°C < T_NTC < 10°C), the warm battery threshold (45°C < T_NTC < 60°C) and the hot battery threshold (T_NTC > 60°C). These temperatures correspond to the V_COLD, V_COOL, V_WARM, and V_HOT thresholds in the EC table. Charging is suspended and timers are suspended when V_TS < V_HOT or V_TS > V_COLD. When V_COOL < V_TS < V_COLD, the charging current is reduced to half of the programmed charge current. When V_HOT < V_TS < V_WARM, the battery regulation voltage is reduced to 4.06V from the 4.2V regulation threshold. The TS function is disabled by connecting TS directly to DRV (V_TS > V_TSOFF).

The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS connected to the center tap to set the threshold. The connections are shown in Figure 13. The resistor values are calculated using the following equations:

Equation 3.

Equation 4.

Where:

V_COLD = 0.60 × V_DRV
V_HOT = 0.30 × V_DRV

Equation 5.

Equation 6.

Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature.

The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using Equation 5 and Equation 6.

Figure 13. TS Circuit

7.4.14 Thermal Regulation and Protection

During the charging process, to prevent overheating in the chip, bq24266 monitors the junction temperature, T_J, of the die and reduces the input current once T_J reaches the thermal regulation threshold, T_REG. The input current is reduced to zero when the junction temperature increases about 10°C above T_REG. Once the input current is reduced to 0, the system current is reduced while the battery supplements the load to supply the system. When the input current is completely reduced to 0 and T_J>125°C, this is may cause a thermal shutdown of the bq24266 if the die temperature rises too high. At any state, if T_J exceeds T_SHTDWN, bq24266 stops charging and disables the buck converter. During thermal shutdown mode, PWM is turned off and all timers are suspended. The charge cycle resumes when T_J falls below T_SHTDWN by approximately 10°C.

7.4.15 Status Outputs (CHG, PG)

The CHG and PG outputs are used to indicate operating conditions for the bq24266. The PG output indicates that a valid input source is connected to V_IN. PG is low when (V_BAT + V_SLP) < V_IN < V_OVP. When there is no supply connected to the input within this range, PG is high impedance. Table 2 illustates the PG behavior under different conditions.

The CHG output indicates new charge cycles. When a new charge cycle is initiated by CE or toggling the input power, CHG goes low and remains low until termination. After termination, CHG remains high impedance until a new charge cycle is initiated or the battery is removed/re-inserted. CHG does not go low during recharge cycles. Table 3 illustrates the CHG behavior under different conditions.

Connect PG and CHG to the DRV output through an LED for visual indication, or connect through a 100kΩ pullup to the required logic rail for host indication.

7.4.16 Boost Mode Operation

When the IUSB inputs are configured in Boost Mode (IUSB3 = 0, IUSB2 = IUSB1 = 1), the device operates in boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB connector.