ZHCSKT7C february   2020  – june 2022 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 LVDS Interface Configuration
        1. 8.9.6.1 LVDS Interface Timings
      7. 8.9.7 General-Purpose Input/Output
        1. 8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.9.8 Camera Serial Interface (CSI)
        1. 8.9.8.1 CSI Switching Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  11. 10Monitoring and Diagnostic Mechanisms
  12. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Imaging Radar using Cascade Configuration
    4. 11.4 Reference Schematic
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 Export Control Notice
    8. 12.8 术语表
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABL|161
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.9.3.1 Clock Specifications

An external crystal is connected to the device pins. Figure 8-4 shows the crystal implementation.

GUID-EDE3039E-2AF2-4B30-B258-B2D36CF1C9A4-low.gifFigure 8-4 Crystal Implementation
Note:

The load capacitors, Cf1 and Cf2 in Figure 8-4, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

Equation 1. GUID-ABEB21DF-C4ED-46A1-8A95-1E534ADF5429-low.gif

Table 8-6 lists the electrical characteristics of the clock crystal.

Table 8-6 Crystal Electrical Characteristics (Oscillator Mode)
NAME DESCRIPTION MIN TYP MAX UNIT
fP Parallel resonance crystal frequency 40 MHz
CL Crystal load capacitance 5 8 12 pF
ESR Crystal ESR 50 Ω
Temperature range Expected temperature range of operation –40 140 °C
Frequency tolerance Crystal frequency tolerance(1)(2) -200 200 ppm
Drive level 50 200 µW
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-7 lists the electrical characteristics of the external clock signal.

Table 8-7 External Clock Mode Specifications
PARAMETER SPECIFICATION UNIT
MIN TYP MAX
Input Clock:
External AC-coupled sine wave or DC-coupled square wave
Phase Noise referred to 40 MHz		 Frequency 40 MHz
AC-Amplitude 700 1200 mV (pp)
DC-trise/fall 10 ns
Phase Noise at 1 kHz –132 dBc/Hz
Phase Noise at 10 kHz –143 dBc/Hz
Phase Noise at 100 kHz –152 dBc/Hz
Phase Noise at 1 MHz –153 dBc/Hz
Duty Cycle 35 65 %
Freq Tolerance –100 100 ppm
Input clock requirements for the Secondary device in cascade mode (assuming the 20Ghz clock is provided from the Primary device) Phase Noise at 10 kHz -127 dBc/Hz
Phase Noise at 100 kHz -137 dBc/Hz
Phase Noise at 1 MHz -147 dBc/Hz
Period jitter @40Mhz 1.75 ps rms
Spur levels (sum of all spurs) -52 dBc