The Processing System in the AWR1443 device is an accelerator for FFT operations. The Radar Hardware Accelerator is an IP that enables off-loading the burden of certain frequently used computations in FMCW radar signal processing from the main processor. It is well-known that FMCW radar signal processing involves the use of FFT and Log-Magnitude computations in order to obtain a radar image across the range, velocity and angle dimensions. Some of the frequently used functions in FMCW radar signal processing can be done within the Radar Hardware Accelerator, while still retaining the flexibility of implementing other proprietary algorithms in the Master System processor.

Key features of the Radar Processing Accelerator are:

• FFT computation, with programmable FFT sizes (powers of 2) up to 1024-pt complex FFT
• Internal FFT bit-width of 24 bits (each for I and Q) for good SQNR performance, with fully programmable butterfly scaling at every radix-2 stage for user flexibility
• Built-in capabilities for simple pre-FFT processing – specifically, programmable windowing, basic interference zeroing-out and basic BPM removal
• Magnitude (absolute value) and Log-Magnitude computation capability
• Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations and transpose accesses as required
• Chaining and Looping mechanism to sequence a set of accelerator operations one-after-another with minimal intervention from the main processor
• CFAR-CA detector support (linear and logarithmic)
• Miscellaneous other capabilities of the accelerator
  • Stitching two or four 1024-point FFTs to get the equivalent of 2048-point or 4096-point FFT for industrial level sensing applications where large FFT sizes are required
  • Slow DFT mode, with resolution equivalent to 16K size FFT, for FFT peak interpolation (eg. range interpolation) purpose
  • Complex Vector Multiplication and Dot product capability for vectors of size up to 512