ZHCS128B May   2011  – October 2015 AMC80

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Level Description
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 Default Interrupt Mode
        2. 7.3.2.2 One-Time Interrupt Mode
        3. 7.3.2.3 Comparator Mode
      3. 7.3.3 Interrupt Structure
    4. 7.4 Programming
      1. 7.4.1 Interface and Control
    5. 7.5 Register Map
      1. 7.5.1  Configuration Register
      2. 7.5.2  Interrupt Status Registers
      3. 7.5.3  Interrupt Mask Registers
      4. 7.5.4  Fan Divisor/RST_OUT/OS Register
      5. 7.5.5  OS Configuration/Temperature Resolution Register
      6. 7.5.6  Conversion Rate Register
      7. 7.5.7  Voltage/Temperature Channel Disable Register
      8. 7.5.8  Input Mode Register
      9. 7.5.9  ADC Control Register
      10. 7.5.10 Conversion Rate Count Register
      11. 7.5.11 Value Ram Register
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Power-On
      2. 8.1.2 Analog Inputs
      3. 8.1.3 Fan Inputs
  9. 器件和文档支持
    1. 9.1 社区资源
    2. 9.2 商标
    3. 9.3 静电放电警告
    4. 9.4 Glossary
  10. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The AMC80 provides seven analog inputs, a temperature sensor, a delta-sigma analog-to-digital converter (ADC), and a variety of inputs and outputs on a single chip. A two-wire SMBus interface is also provided. The AMC80 can continuously perform power-supply, temperature, and fan monitoring for a variety of applications. The AMC80 is fully pin- and software-compatible with the LM96080 and LM80.

Functional Block Diagram

AMC80 fbd_high-level_bos559.gif

Feature Description

Block Level Description

The AMC80 continuously converts analog inputs to 10-bit resolution using a 2.5-mV least significant bit (LSB) with a default input range of 0 V to 2.56 V, or a 6-mV LSB with a programmable input range of 0 V to V+. The analog inputs (CH0 to CH6) are intended for connection to the several power supplies present in any typical system. Temperature can be converted to a 9-bit or 12-bit resolution with either 0.5°C or 0.0625°C LSB, respectively. The FAN1 and FAN2 inputs can be programmed to accept either a fan failure indicator or tachometer signals. Fan failure signals can be programmed to be either active high or active low. Fan inputs measure the period of tachometer pulses from the the fans, providing a higher count for lower fan speeds. The fan inputs are digital inputs with transition levels according to the Digital Inputs section of the Electrical Characteristics table. Full-scale fan counts are 255 (8-bit counter), which represent a stopped or very slow fan. Nominal speeds, based on a count of 153, are programmable from 1100 RPM to 8800 RPM. Signal conditioning circuitry is included to accommodate slow rise and fall times.

The AMC80 provides a number of internal registers:

  • Configuration Register: Provides control and configuration.
  • Interrupt Status Registers: Two registers that provide the status of each interrupt alarm.
  • Interrupt Mask Registers: Allows masking of individual interrupt sources, as well as separate masking for both hardware interrupt outputs.
  • Fan Divisor/RST_OUT/OS Register: Bits 0 to 5 of this register contain the divisor bits for the FAN1 and FAN2 inputs. Bits 6 and 7 control the function of the RST_OUT/OS output.
  • OS Configuration/Temperature Resolution Register: The configuration of the overtemperature shutdown (OS) is controlled by the lower three bits of this register. Bit 3 enables 12-bit temperature conversions. In 12-bit mode, bits 4 to 7 represent the four LSBs of the temperature measurement. In 9-bit mode, bit 4 represents the LSB of the temperature measurement.
  • Conversion Rate Register: Sets the time interval of the continuous monitoring cycle to either fixed or programmable (see the Conversion Rate Count Register for setting the programmable time interval).
  • Voltage/Temperature Channel Disable Register: Allows voltage inputs and the local temperature conversion to be disabled.
  • Input Mode Register: Allows voltage inputs to be configured as single-ended or as a differential pair with normal or reverse polarity.
  • ADC Control Register: Bits 0 to 2 set the programmable conversion rate for the 10-bit ADC. Bits 3 to 5 allow for programmable input full-scale voltage.
  • Conversion Rate Count Register: Selects the adjustable time interval when the conversion rate of the continuous monitoring cycle is set to programmable.
  • Value RAM: The monitoring results (for temperature, voltages, fan counts, and Fan Divisor/RST_OUT/OS Register limits) are all contained in the Value RAM. The Value RAM consists of 32 bytes. The first 10 bytes are all of the results, the next 20 bytes are the interrupt alarm limits, and the last two bytes are at the upper locations for manufacturer ID and die revision ID.

The AMC80 SMBus is compatible with both fast mode (400 kHz) and high-speed mode (3.4 MHz) two-wire interface modes of operation. The AMC80 supports a timeout reset function on SDA and SCL that prevents two-wire bus lockup, and includes an analog filter on the two-wire digital control lines that improves noise immunity. Three address pins (A0 to A2), allow up to eight devices on a single bus. When enabled, the AMC80 starts by cycling through each measurement in sequence, and continuously loops through the sequence based on the Conversion Rate Register (address 07h) setting. Each measured value is compared to values stored in the Value RAM Registers (addresses 2Ah to 3Dh). When the measured value exceeds the programmed limit, the AMC80 sets a corresponding interrupt in the Interrupt Status Registers (addresses 01h and 02h). Two output interrupt lines (INT and RST_OUT/OS) are available. INT is fully programmable with the ability to mask each interrupt source and each output. The Fan Divisor/RST_OUT/OS Register (address 05h) has control bits that enable or disable the hardware interrupts. Additional digital inputs are provided for daisy-chaining the interrupt output pin, INT. This configuration is achieved by connecting multiple external temperature sensors (for example, the TMP75) to the board temperature interrupt (BTI) input and/or the GPI/CI input. The chassis intrusion (CI) input is designed to accept an active high signal from an external circuit that latches (for example, when the chassis from a server rack is removed).

Temperature Measurement

The AMC80 ΔVBE-type temperature sensor, is a ΔΣ ADC that performs 9-bit or 12-bit twos complement temperature conversions. An 8-bit comparator that compares the readings to the user-programmable hot and overtemperature setpoints, and hysteresis values is also incorporated into the AMC80.

Temperature data can be read from the Temperature Reading Register (address 27h). Temperature limits can be read from and written to the Hot Temperature (THOT), Hot Temperature Hysteresis (THOT_HYST), OS Temperature (TOS), and OS Temperature Hysteresis (TOS_HYST) Limit Registers (addresses 38h to 3Bh). Each limit is represented in 12-bit, 9-bit, or 8-bit resolution, as shown in Table 1.

Table 1. Temperature Lookup

TEMPERATURE 12-BIT DIGITAL OUTPUT (HEX)
LSB = 0.0625°C
9-BIT DIGITAL OUTPUT (HEX)
LSB = 0.5°C
8-BIT DIGITAL OUTPUT (HEX)
LSB = 1°C
+125°C 07D 0FA 7D
+25°C 019 032 19
+1°C 010 003 01
0.0625°C 001
0°C 000 000 00
–0.0625°C FFF
–1°C FF0 1FF FF
–25°C E70 1CE E7
–55°C C90 192 C9

When using a single-byte read, the eight MSBs of the temperature reading can be found in the Value RAM Register (address 27h). The remainder of the temperature reading can be found in the OS Configuration/Temperature Resolution Register (address 06h), bits 4 to 7. In 9-bit format, bit 7 is the only valid bit. In addition, all nine or 12 bits can be read using a double-byte read at register address 27h.

There are four Value RAM Register limits for the temperature reading that affect the INT and OS outputs of the AMC80. These are the THOT, THOT_HYST, TOS, TOS_HYST Limit Registers (addresses 38h to 3Bh); see Table 15. There are three interrupt modes of operation: Default Interrupt, One-Time Interrupt, and Comparator. The OS output of the AMC80 can be programmed for One-Time Interrupt mode and Comparator mode. INT can be programmed for Default Interrupt mode and One-Time Interrupt mode. These modes are explained in the following subsections.

Default Interrupt Mode

In Default Interrupt mode, exceeding THOT causes an interrupt that remains active indefinitely until reset by reading Interrupt Status Register 1 (address 01h) or cleared by the INT_Clear bit in the Configuration Register (address 00h, bit 3). When an interrupt event has occurred by exceeding THOT, and is then reset, another interrupt occurs again when the next temperature conversion has completed. The interrupts continue to occur in this manner until the temperature falls below THOT_HYST, at which time the interrupt output automatically clears.

One-Time Interrupt Mode

In One-Time Interrupt mode, exceeding THOT causes an interrupt that remains active indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the Configuration Register. When an interrupt event has occurred by exceeding THOT, and is then reset, an interrupt does not occur again until the temperature falls below THOT_HYST.

Comparator Mode

In Comparator mode, exceeding TOS causes the OS output to go low (default) and remain low until the temperature falls below TOS_HYST. When the temperature falls below TOS_HYST, OS goes high.

Interrupt Structure

Figure 7 depicts the interrupt structure of the AMC80.

AMC80 ai_int_structure_bos559.gif Figure 7. Interrupt Structure

External interrupt inputs can come from the following sources:

  • Board Temperature Interrupt (BTI) - This pin is an active low interrupt recommended to come from the overtemperature shutdown (OS) output of TMP75 temperature sensors. The TMP75 OS output activates when its temperature exceeds a programmed threshold. If the temperature of any TMP75 exceeds its programmed limit, BTI is driven low. This action generates an interrupt through bit 1 of Interrupt Status Register 2 (address 02h) that notifies the host of a possible overtemperature condition. To disable this feature, set bit 1 of Interrupt Mask Register 2 (address 04h) to high. This pin also provides an internal, 10-kΩ pull-up resistor.
  • GPI/CI - This pin is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This action could be accomplished mechanically, optically, or electrically; circuitry external to the AMC80 is expected to latch the event. Read this interrupt using bit 4 of Interrupt Status Register 2 (address 02h), and disable it using bit 4 of Interrupt Mask Register 2 (address 04h). The design of the AMC80 allows this input to go high even with no power applied, and no clamping or other interference with the line occurs. This line can also be pulled low by the AMC80 for at least 10ms to reset a typical chassis-intrusion circuit. Accomplish this reset by setting bit 5 of the Configuration Register (address 00h) to high; this bit is self-clearing.
  • INT_IN - This pin is an active low interrupt that provides a way to connect an INT from other devices through the AMC80 to the processor. If this pin is pulled low, then bit 7 of Interrupt Status Register 1 (address 01h) goes high, indicating this interrupt detection. Setting bit 1 of the Configuration Register (address 00h) also allows the INT pin to go low when INT_IN goes low. To disable this feature, set bit 7 of Interrupt Mask Register 1 (address 03h) to high.

Device interrupt outputs can come from the following sources:

  • INT - This pin becomes active whenever INT_IN, BTI, or GPI/CI interrupts. INT is enabled when bit 1 of the Configuration Register (address 00h) is set high. Bits 2 and 3 of the Configuration Register are also used to set the polarity and state of the INT interrupt line.
  • OS - In the Fan Divisor/RST_OUT/OS Register (address 05h), bit 6 (OS Pin Enable), must be set high and bit 7 (RST Enable) must be set to low in order to enable the OS function on the RST_OUT/OS pin. The OS pin has two modes of operation: One-Time Interrupt and Comparator. One-Time Interrupt mode is selected by taking bit 2 of the OS Configuration/Temperature Resolution Register (address 06h) high. If bit 2 is taken low, then Comparator mode is selected. Unlike the OS pin, the OS bit in Interrupt Status Register 2 (address 02h, bit 5) functions in Default Interrupt and One-Time Interrupt modes. The OS bit can be masked to the INT pin by taking bit 5 in Interrupt Mask Register 2 (address 04h) low.

Reading the Interrupt Status Registers (addresses 01h to 02h) outputs the contents and then resets the registers and the INT pin. The INT pin is also cleared by the INT_Clear bit (address 00h, bit 3) without affecting the contents of the Interrupt Status Registers. When this bit is high, the AMC80 monitoring loop is inactive; monitoring resumes when this bit is low.

Programming

Interface and Control

The SMBus control lines in the AMC80 include SDA, SCL, and the A0 to A2 address pins, which allow up to eight AMC80 devices to be on the same bus. The AMC80 can only operate as a slave device. The SCL line controls only the serial interface; all other clock-related functions within the AMC80 (such as the ADC and fan counters) operate with a separate asynchronous internal clock. The default power-on SMBus address for the AMC80 is '0101'(A2)(A1)(A0) binary, where (A2)(A1)(A0) is the SMBus address.

When using the SMBus interface, a write command always consists of the AMC80 SMBus interface address byte, followed by the internal address register byte, and then the data byte (see Figure 8).

See Figure 9 for the read operation timing. There are two cases for a read operation:

  1. If the contents of the Internal Address Register are known, simply read the AMC80 with the SMBus interface address byte, followed by the data byte read from the ADC80.
  2. If the internal Address Register contents are unknown, write to the AMC80 with the SMBus interface address byte, followed by the internal address register bye. Then restart the serial communication with a read that consist of the SMBus interface address byte, followed by the data byte read from the AMC80.

Table 2. Register Overview

REGISTER INTERNAL
ADDRESS
(HEX)
POWER-ON
VALUE
(HEX)
NOTES
Configuration Register 00 08
Interrupt Status Register 1 01 xx Indeterminate
Interrupt Status Register 2 02 xx Indeterminate
Interrupt Mask Register 1 03 00
Interrupt Mask Register 2 04 00
Fan Divisor/RST_OUT/OS Register 05 14 FAN1 and FAN2 divisor = 2 (count of 153 = 4400 RPM)
OS Configuration/Temperature Resolution Register 06 x1 Four MSBs are indeterminate
Conversion Rate Register 07 40
Voltage/Temperature Channel Disable Register 08 00 Allows voltage monitoring inputs to be disabled
Input Mode Register 09 00
ADC Control Register 0A 02
Conversion Rate Count Register 0B 40
Value RAM Register 20 to 29 xx Indeterminate
Value RAM Register 2A to 3D xx Indeterminate
Value RAM Register 3E 80
Value RAM Register 3F 09
AMC80 ai_two_wire_write_bos559.gif
The values of A0, A1, and A2 are determined by the A0, A1, and A2 pins, respectively.
Figure 8. Two-Wire Timing for Write Word Format
AMC80 ai_two_wire_read_bos559.gif
The values of A0, A1, and A2 are determined by the A0, A1, and A2 pins, respectively.
Master should leave SDA high to terminate a single-byte read operation.
Master should leave SDA high to terminate a two-byte read operation.
Figure 9. Two-Wire Timing for Read Word Format

Register Map

Configuration Register

Table 3. Configuration Register (Address = 00h, Default = 08h)

BIT NAME TYPE DESCRIPTION
0 Start R/W '1' enables startup of monitoring activity; '0' puts device in shutdown mode.
1 INT Enable R/W '1' enables the INT output.
2 INT Polarity Select R/W '1' selects active-high, open-source output; '0' selects active-low, open-drain output.
3 INT_Clear R/W '1' disables the INT output without affecting the contents of the Interrupt Status Registers. The device stops monitoring and resumes on a '0'.
4 RESET R/W '1' outputs an active-low reset signal at RST_OUT, if bit 7 and bit 6 in the Fan Divisor/ Register (address 05h) are set to '1' and '0', respectively. This bit is cleared when the pulse becomes inactive.
5 Chassis Clear R/W '1' clears the GPI/CI pin. This bit clears itself after 10ms.
6 GPO R/W '1' drives the GPO pin low.
7 INITIALIZATION R/W '1' restores power-on-default values to the registers. This bit is self-clearing

Interrupt Status Registers

Table 4. Interrupt Status Register 1 (Address = 01h, Default = xxh; see Table 2)

BIT NAME TYPE DESCRIPTION
0 CH0 Read '1' indicates a high or low limit has been exceeded.
1 CH1 Read '1' indicates a high or low limit has been exceeded.
2 CH2 Read '1' indicates a high or low limit has been exceeded.
3 CH3 Read '1' indicates a high or low limit has been exceeded.
4 CH4 Read '1' indicates a high or low limit has been exceeded.
5 CH5 Read '1' indicates a high or low limit has been exceeded.
6 CH6 Read '1' indicates a high or low limit has been exceeded.
7 INT_IN Read '1' indicates that a low signal has been detected on the INT_IN pin.

Table 5. Interrupt Status Register 2 (Address = 02h, Default = xxh; see Table 2)

BIT NAME TYPE DESCRIPTION
0 Hot Temperature Read '1' indicates a high or low limit has been exceeded. One-Time Interrupt and Default Interrupt modes are supported and can be set by bit 6 of Interrupt Mask Register 2 (address 04h).
1 BTI Read '1' indicates that an interrupt has occurred from the BTI input pin.
2 FAN 1 Read '1' indicates that a fan count limit has been exceeded.
3 FAN 2 Read '1' indicates that a fan count limit has been exceeded.
4 GPI/CI Read '1' indidates that GPI/CI has gone high.
5 OS Read '1' indicates a high or low temperature limit has been exceeded. One-Time Interrupt and Default Interrupt modes are supported and can be set by bit 7 of Interrupt Mask Register 2 (address 04h).
6 Reserved Read This bit is reserved.
7 Reserved Read This bit is reserved.

Interrupt Mask Registers

Table 6. Interrupt Mask Register 1 (Address = 03h, Default = 00h)

BIT NAME TYPE DESCRIPTION
0 CH0 R/W '1' disables the corresponding interrupt status bit in Table 4 to trigger the INT interrupt.
1 CH1 R/W
2 CH2 R/W
3 CH3 R/W
4 CH4 R/W
5 CH5 R/W
6 CH6 R/W
7 INT_IN R/W

Table 7. Interrupt Mask Register 2 (Address = 04h, Default = 00h)

BIT NAME TYPE DESCRIPTION
0 Hot Temperature R/W '1' disables the corresponding interrupt status bit in Table 5 to trigger the INT interrupt.
1 BTI R/W
2 FAN 1 R/W
3 FAN 2 R/W
4 GPI/CI R/W
5 OS R/W
6 INT Interrupt Mode Select R/W '0' selects Default Interrupt mode. '1' selects One-Time Interrupt mode.
7 OS Interrupt Mode Select R/W '0' selects Comparator mode. '1' selects One-Time Interrupt mode.

Fan Divisor/RST_OUT/OS Register

Table 8. Fan Divisor/RST_OUT/OS Register (Address = 05h, Default = 14h)

BIT NAME TYPE DESCRIPTION
0 FAN1 Mode Select R/W '1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN1 input.
1 FAN2 Mode Select R/W '1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN2 input.
2 FAN1 RPM Control 1 R/W FAN1 speed control:
'00' = divide by 1.
'01' = divide by 2.
'10' = divide by 4.
'11' = divide by 8.
If level-sensitive input is selected, '01' selects an active-low input and '00' selects an active-high input.
3 FAN1 RPM Control 0 R/W
4 FAN2 RPM Control 1 R/W FAN2 speed control:
'00' = divide by 1.
'01' = divide by 2.
'10' = divide by 4.
'11' = divide by 8.
If level select input is selected, '01' selects an active-low input and '00' selects an active-high input.
5 FAN2 RPM Control 0 R/W
6 OS Pin Enable R/W '1' enables OS mode on the RST_OUT/OS pin when bit 7 is set to '0'.
NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.
7 RST_OUT Pin Enable R/W '1' enables RST_OUT mode on the RST_OUT/OS pin when bit 6 is set to '0'.
NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.

OS Configuration/Temperature Resolution Register

Table 9. OS Configuration/Temperature Resolution Register (Address = 06h, Default = x1h; see Table 2)

BIT NAME TYPE DESCRIPTION
0 OS Status Read This bit mirrors the state of the RST_OUT/OS pin when in OS mode.
1 OS Polarity R/W '1' selects OS to be active-high '0' selects OS to be active-low.
2 OS Mode Select R/W '1' selects One-Time-Interrupt mode; '0' selects Comparator mode.
3 Temperature Resolution Control R/W '1' selects 11-bit plus sign resolution temperature conversion; '0' selects the default 8-bit plus sign resolution temperature conversion.
4 Temp3 R/W The lower four LSBs of the 11-bit plus sign temperature data. For 8-bit plus sign temperature data, bit 7 is the LSB and bits 4 to 6 are undefined.
5 Temp2 R/W
6 Temp1 R/W
7 Temp0 R/W

Conversion Rate Register

Table 10. Conversion Rate Register (Address = 07h, Default = 40h)

BIT NAME TYPE DESCRIPTION
0 CR1 R/W Controls conversion rate:
'0' = Programmable conversion rate by the following formula:
Monitoring delay = (ms) = 1.42 × (8 × N + 6)
where N can be set by bits 7:0 in the Conversion Rate Count Register (address 0Bh).
'1' = Continuous conversion.
1 Reserved R/W '0' must be written to this bit.
2 Reserved R/W '0' must be written to this bit.
3 Reserved R/W '0' must be written to this bit.
4 Reserved R/W '0' must be written to this bit.
5 Reserved R/W '0' must be written to this bit.
6 Reserved R/W '0' must be written to this bit.
7 Reserved R/W '0' must be written to this bit.

Voltage/Temperature Channel Disable Register

Table 11. Voltage/Temperature Channel Disable Register (Address = 08h, Default = 00h)

BIT NAME TYPE DESCRIPTION
0 CH0 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH0.
1 CH1 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH1.
2 CH2 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH2.
3 CH3 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH3.
4 CH4 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH4.
5 CH5 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH5.
6 CH6 R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for CH6.
7 Temp R/W '1' disables conversions and suppresses error events; Value RAM Register reads '0' for temperature.

Input Mode Register

Table 12. Input Mode Register (Address = 09h, Default = 00h)

BIT NAME TYPE DESCRIPTION
0 Diff01 R/W When set to '1', CH0 and CH1 operate as a differential input.
When set to '0', CH0 and CH1 operate as 2 single-ended inputs.
1 Pol01 R/W When bit 0 = '1', CH0 and CH1 differential inputs are setup in normal polarity mode when this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.
When bit 0 is set to “0”, this bit is ignored.
2 Diff23 R/W When set to '1', CH2 and CH3 operate as a differential input.
When set to '0', CH2 and CH3 operate as 2 single-ended inputs.
3 Pol23 R/W When bit 0 = '1', CH2 and CH3 differential inputs are setup in normal polarity mode when this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.
When bit 0 is set to “0”, this bit is ignored.
4 Diff45 R/W When set to '1', CH4 and CH5 operate as a differential input.
When set to '0', CH4 and CH5 operate as 2 single-ended inputs.
5 Pol45 R/W When bit 0 = '1', CH4 and CH5 differential inputs are setup in normal polarity mode when this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.
When bit 0 is set to “0”, this bit is ignored.
6 Reserved R/W '0' must be written to this bit.
7 Reserved R/W '0' must be written to this bit.

ADC Control Register

Table 13. ADC Control Register (Address = 0Ah, Default = 02h)

BIT NAME TYPE DESCRIPTION
0 DR2 R/W The 10-bit ADC conversion rate for the analog inputs is set as follows:
000 = 0.512 kHz
001 = 1 kHz
010 = 1.98 kHz
011 = 3.6 kHz
100 = 6.3 kHz
101 = 9.8 kHz
110 = 13.15 kHz
111 = 13.15 kHz
1 DR1 R/W
2 DR0 R/W
3 PGA2 R/W The full-scale analog input range is set as follows:
000 = 2.56 V
001 = VDD
010 = 4.096 V or VDD (whichever is less)
011 = 2.048 V
100 = 1.024 V
101 = 0.512 V
110 = 0.256 V
111 = 0.256 V
4 PGA1 R/W
5 PGA0 R/W
6 Reserved R/W '0' must be written to this bit.
7 Reserved R/W '0' must be written to this bit.

Conversion Rate Count Register

Table 14. Conversion Rate Count Register (Address = 0Bh, Default = 40h)

BIT NAME TYPE DESCRIPTION
0 CRC7 R/W When bit 0 of the Conversion Rate Register (address 07h) is set to '0', the monitoring conversion delay can be programmed as follows:
0000000 = 0
0000001 = 1
0000010 = 2
… … …
1111111 = 255
When bit 0 of the Conversion Rate Register is set to '1', these bits are ignored.
1 CRC6 R/W
2 CRC5 R/W
3 CRC4 R/W
4 CRC3 R/W
5 CRC2 R/W
6 CRC1 R/W
7 CRC0 R/W

Value Ram Register

Table 15. Value RAM Register (Addresses = 20h to 3Fh)

ADDRESS (HEX) DESCRIPTION
20 CH0 reading (10-bit)
21 CH1 reading (10-bit)
22 CH2 reading (10-bit)
23 CH3 reading (10-bit)
24 CH4 reading (10-bit)
25 CH5 reading (10-bit)
26 CH6 reading (10-bit)
27 Temperature reading (9-bit or 12-bit for easy readback)
28 FAN1 reading
29 FAN2 reading
2A CH0 high limit
2B CH0 low limit
2C CH1 high limit
2D CH1 low limit
2E CH2 high limit
2F CH2 low limit
30 CH3 high limit
31 CH3 low limit
32 CH4 high limit
33 CH4 low limit
34 CH5 high limit
35 CH5 low limit
36 CH6 high limit
37 CH6 low limit
38 Hot temperature high limit (THOT)
39 Hot temperature hysteresis low limit (THOT_HYST)
3A OS temperature high limit (TOS)
3B OS temperature hysteresis low limit (TOS_HYST)
3C FAN1 fan count limit
3D FAN2 fan count limit
3E Manufacturer ID (always defaults to 80h)
3F Die revision ID (always defaults to 08h)