ZHCSID7 June   2018 ADS8688AT

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: Serial Interface
    7. 6.7 Switching Characteristics: Serial Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST/PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
    5. 7.5 Register Maps
      1. 7.5.1 Command Register Description
      2. 7.5.2 Program Register Description
        1. 7.5.2.1 Program Register Read/Write Operation
        2. 7.5.2.2 Program Register Map
        3. 7.5.2.3 Program Register Descriptions
          1. 7.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 7.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
              1. Table 11. AUTO_SEQ_EN Field Descriptions
            2. 7.5.2.3.1.2 Channel Power Down Register (address = 02h)
              1. Table 12. Channel Power Down Register Field Descriptions
          2. 7.5.2.3.2 Device Features Selection Control Register (address = 03h)
            1. Table 13. Feature Select Register Field Descriptions
          3. 7.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
            1. Table 16. Channel n Input Range Registers Field Descriptions
          4. 7.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 7.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
              1. Table 17. ALARM Overview Tripped-Flag Register Field Descriptions
            2. 7.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
              1. Table 18. ALARM Ch0-3 Tripped-Flag Register Field Descriptions
              2. Table 19. ALARM Ch0-3 Active-Flag Register Field Descriptions
              3. Table 20. ALARM Ch4-7 Tripped-Flag Register Field Descriptions
              4. Table 21. ALARM Ch4-7 Active-Flag Register Field Descriptions
          5. 7.5.2.3.5 Alarm Threshold Setting Registers
            1. Table 22. Channel n Hysteresis Register Field Descriptions (n = 0 to 7)
            2. Table 23. Channel n High Threshold MSB Register Field Descriptions (n = 0 to 7)
            3. Table 24. Channel n High Threshold LSB Register Field Descriptions (n = 0 to 7)
            4. Table 25. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
            5. Table 26. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
          6. 7.5.2.3.6 Command Read-Back Register (address = 3Fh)
            1. Table 27. Command Read-Back Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.8 Typical Characteristics

at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
ADS8688AT C001_SBAS680.png
Figure 2. Input I-V Characteristic
ADS8688AT D005_SBAS813.gif
All input ranges
Figure 4. Input Impedance Variation vs Temperature
ADS8688AT C007_SBAS680.png
Mean = 32768.67, sigma = 0.58, input = 0 V,
range = ±2.5 × VREF
Figure 6. DC Histogram for Mid-Scale Inputs
(±2.5 × VREF)
ADS8688AT C009_SBAS680.png
Mean = 32768.8, sigma = 0.76, input = 0 V,
range = ±0.625 × VREF
Figure 8. DC Histogram for Mid-Scale Inputs
(±0.625 × VREF)
ADS8688AT C011_SBAS680.png
Mean = 32768.2, sigma = 0.75, input = 0.625 × VREF,
range = 1.25 × VREF
Figure 10. DC Histogram for Mid-Scale Inputs
(1.25 × VREF)
ADS8688AT C013_SBAS680.png
Mean = 32768.5, sigma = 2.68, input = 0 V,
range = ±0.15625 × VREF
Figure 12. DC Histogram for Mid-Scale Inputs
(±0.15625 × VREF)
ADS8688AT C015_SBAS680.png
Mean = 32768.5, sigma = 2.68, input = 0.15625 × VREF,
range = 0.3125 × VREF
Figure 14. DC Histogram for Mid-Scale Inputs
(0.3125 × VREF)
ADS8688AT D017_SBAS813.gif
All input ranges
Figure 16. DNL vs Temperature
ADS8688AT C019_SBAS680.png
Range = ±1.25 × VREF
Figure 18. Typical INL for All Codes
ADS8688AT C021_SBAS680.png
Range = 2.5 × VREF
Figure 20. Typical INL for All Codes
ADS8688AT C023_SBAS680.png
Range = ±0.3125 × VREF
Figure 22. Typical INL for All Codes
ADS8688AT C025_SBAS680.png
Range = 0.625 × VREF
Figure 24. Typical INL for All Codes
ADS8688AT D027_SBAS813.gif
Range = ±2.5 × VREF
Figure 26. INL vs Temperature (±2.5 × VREF)
ADS8688AT D029_SBAS813.gif
Range = ±0.625 × VREF
Figure 28. INL vs Temperature (±0.625 × VREF)
ADS8688AT D031_SBAS813.gif
Range = 1.25 × VREF
Figure 30. INL vs Temperature (1.25 × VREF)
ADS8688AT D033_SBAS813.gif
Range = ±0.15625 × VREF
Figure 32. INL vs Temperature (±0.15625 × VREF)
ADS8688AT D035_SBAS813.gif
Range = 0.3125 × VREF
Figure 34. INL vs Temperature (0.3125 × VREF)
ADS8688AT C037_SBAS680.png
Range = ±2.5 × VREF
Figure 36. Typical Histogram for Offset Drift
ADS8688AT D039_SBAS813.gif
Figure 38. Gain Error vs Temperature Across Input Ranges
ADS8688AT D041_SBAS813.gif
Range = ±2.5 × VREF
Figure 40. Gain Error vs Temperature Across Channels
ADS8688AT C043_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 92.3 dB,
SINAD = 91.9 dB, THD = 101 dB, SFDR = 104 dB
Figure 42. Typical FFT Plot (±2.5 × VREF)
ADS8688AT C045_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = 106 dB, SFDR = 107 dB
Figure 44. Typical FFT Plot (±0.625 × VREF)
ADS8688AT C047_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = –106 dB, SFDR = 107 dB
Figure 46. Typical FFT Plot (1.25 × VREF)
ADS8688AT C049_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 77.6 dB,
SINAD = 77.6 dB, THD = –106 dB, SFDR = 107 dB
Figure 48. Typical FFT Plot (±0.15625 × VREF)
ADS8688AT C051_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 77.55 dB,
SINAD = 77.5 dB, THD = –100 dB, SFDR = 107 dB
Figure 50. Typical FFT Plot (0.3125 × VREF)
ADS8688AT D053_SNR_SBAS813.gif
fIN = 1 kHz
Figure 52. SNR vs Temperature
ADS8688AT D055_SINAD_SBAS813.gif
fIN = 1 kHz
Figure 54. SINAD vs Temperature
ADS8688AT D057_SBAS813.gif
fIN = 1 kHz
Figure 56. THD vs Temperature
ADS8688AT C059_SBAS680.png
Figure 58. Isolation Crosstalk vs Frequency
ADS8688AT C061_SBAS680.png
Input = 2 × maximum input voltage
Figure 60. Isolation Crosstalk vs Frequency for
Overrange Inputs
ADS8688AT D075_SBAS813.gif
Figure 62. AVDD Current vs Temperature
(During Sampling)
ADS8688AT D077_SBAS813.gif
Figure 64. AVDD Current vs Temperature
(Power Down)
ADS8688AT D002_SBAS813.gif
Input range = ±2.5 × VREF
Figure 3. Input Current vs Temperature
ADS8688AT C006_SBAS680.png
Number of samples = 1160
Figure 5. Typical Distribution of Input Impedance
ADS8688AT C008_SBAS680.png
Mean = 32768.60, sigma = 0.63, input = 0 V,
range = ±1.25 × VREF
Figure 7. DC Histogram for Mid-Scale Inputs
(±1.25 × VREF)
ADS8688AT C010_SBAS680.png
Mean = 32767.75, sigma = 0.65, input = 1.25 × VREF,
range = 2.5 × VREF
Figure 9. DC Histogram for Mid-Scale Inputs
(2.5 × VREF)
ADS8688AT C012_SBAS680.png
Mean = 32768.5, sigma = 1.30, input = 0 V,
range = ±0.3125 × VREF
Figure 11. DC Histogram for Mid-Scale Inputs
(±0.3125 × VREF)
ADS8688AT C014_SBAS680.png
Mean = 32768.5, sigma = 1.30, input = 0.3125 × VREF,
range = 0.625 × VREF
Figure 13. DC Histogram for Mid-Scale Inputs
(0.625 × VREF)
ADS8688AT C016_SBAS680.png
All input ranges
Figure 15. Typical DNL for All Codes
ADS8688AT C018_SBAS680.png
Range = ±2.5 × VREF
Figure 17. Typical INL for All Codes
ADS8688AT C020_SBAS680.png
Range = ±0.625 × VREF
Figure 19. Typical INL for All Codes
ADS8688AT C022_SBAS680.png
Range = 1.25 × VREF
Figure 21. Typical INL for All Codes
ADS8688AT C024_SBAS680.png
Range = ±0.15625 × VREF
Figure 23. Typical INL for All Codes
ADS8688AT C026_SBAS680.png
Range = 0.3125 × VREF
Figure 25. Typical INL for All Codes
ADS8688AT D028_SBAS813.gif
Range = ±1.25 × VREF
Figure 27. INL vs Temperature (±1.25 × VREF)
ADS8688AT D030_SBAS813.gif
Range = 2.5 × VREF
Figure 29. INL vs Temperature (2.5 × VREF)
ADS8688AT D032_SBAS813.gif
Range = ±0.3125 × VREF
Figure 31. INL vs Temperature (±0.3125 × VREF)
ADS8688AT D034_SBAS813.gif
Range = 0.625 × VREF
Figure 33. INL vs Temperature (0.625 × VREF)
ADS8688AT D036_SBAS813.gif
Figure 35. Offset Error vs
Temperature Across Input Ranges
ADS8688AT D038_SBAS813.gif
Range = ±2.5 × VREF
Figure 37. Offset Error vs Temperature Across Channels
ADS8688AT C040_SBAS680.png
Range = ±2.5 × VREF
Figure 39. Typical Histogram for Gain Error Drift
ADS8688AT C042_SBAS680.png
Figure 41. Gain Error vs External Resistance (REXT)
ADS8688AT C044_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 91.4 dB,
SINAD = 91.2 dB, THD = 105 dB, SFDR = 107 dB
Figure 43. Typical FFT Plot (±1.25 × VREF)
ADS8688AT C046_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 90.93 dB,
SINAD = 90.48 dB, THD = 100 dB, SFDR = 102 dB
Figure 45. Typical FFT Plot (2.5 × VREF)
ADS8688AT C048_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 83.55 dB,
SINAD = 83.5 dB, THD = –104 dB, SFDR = 107 dB
Figure 47. Typical FFT Plot (±0.3125 × VREF)
ADS8688AT C050_SBAS680.png
Number of points = 64k, fIN = 1 kHz, SNR = 83.55 dB,
SINAD = 83.5 dB, THD = –103 dB, SFDR = 107 dB
Figure 49. Typical FFT Plot (0.625 × VREF)
ADS8688AT C052_SBAS680.png
Figure 51. SNR vs Input Frequency
ADS8688AT C054_SBAS680.png
Figure 53. SINAD vs Input Frequency
ADS8688AT C056_SBAS680.png
Figure 55. THD vs Input Frequency
ADS8688AT C058_SBAS680.png
Figure 57. Memory Crosstalk vs Frequency
ADS8688AT C060_SBAS680.png
Input = 2 × maximum input voltage
Figure 59. Memory Crosstalk vs Frequency for
Overrange Inputs
ADS8688AT D074_SBAS813.gif
Figure 61. AVDD Current vs Temperature
(fS = 500 kSPS)
ADS8688AT D076_SBAS813.gif
Figure 63. AVDD Current vs Temperature
(STANDBY)