ZHCSDW1 July   2015 ADS8684A , ADS8688A

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
      2. 8.3.2  Analog Input Impedance
      3. 8.3.3  Input Overvoltage Protection Circuit
      4. 8.3.4  Programmable Gain Amplifier (PGA)
      5. 8.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 8.3.6  ADC Driver
      7. 8.3.7  Multiplexer (MUX)
      8. 8.3.8  Reference
        1. 8.3.8.1 Internal Reference
        2. 8.3.8.2 External Reference
      9. 8.3.9  Auxiliary Channel
        1. 8.3.9.1 Input Driver for the AUX Channel
      10. 8.3.10 ADC Transfer Function
      11. 8.3.11 Alarm Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface
        1. 8.4.1.1 Digital Pin Description
          1. 8.4.1.1.1 CS (Input)
          2. 8.4.1.1.2 SCLK (Input)
          3. 8.4.1.1.3 SDI (Input)
          4. 8.4.1.1.4 SDO (Output)
          5. 8.4.1.1.5 DAISY (Input)
          6. 8.4.1.1.6 RST/PD (Input)
        2. 8.4.1.2 Data Acquisition Example
        3. 8.4.1.3 Host-to-Device Connection Topologies
          1. 8.4.1.3.1 Daisy-Chain Topology
          2. 8.4.1.3.2 Star Topology
      2. 8.4.2 Device Modes
        1. 8.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 8.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 8.4.2.3 STANDBY Mode (STDBY)
        4. 8.4.2.4 Power-Down Mode (PWR_DN)
        5. 8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)
        6. 8.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 8.4.2.7 Channel Sequencing Modes
        8. 8.4.2.8 Reset Program Registers (RST)
    5. 8.5 Register Maps
      1. 8.5.1 Command Register Description
      2. 8.5.2 Program Register Description
        1. 8.5.2.1 Program Register Read/Write Operation
        2. 8.5.2.2 Program Register Map
        3. 8.5.2.3 Program Register Descriptions
          1. 8.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 8.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
            2. 8.5.2.3.1.2 Channel Power Down Register (address = 02h)
          2. 8.5.2.3.2 Device Features Selection Control Register (address = 03h)
          3. 8.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
          4. 8.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 8.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
            2. 8.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          5. 8.5.2.3.5 Alarm Threshold Setting Registers
          6. 8.5.2.3.6 Command Read-Back Register (address = 3Fh)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档 
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Detailed Description

8.1 Overview

The ADS8684A and ADS8688A are 16-bit data acquisition systems with 4- and 8-channel analog inputs, respectively. Each analog input channel consists of an overvoltage protection circuit, a programmable gain amplifier (PGA), and a second-order, antialiasing filter that conditions the input signal before being fed into a 4- or 8-channel analog multiplexer (MUX). The output of the MUX is digitized using a 16-bit analog-to-digital converter (ADC), based on the successive approximation register (SAR) architecture. This overall system can achieve a maximum throughput of 500 kSPS, combined across all channels. The devices feature a 4.096-V internal reference with a fast-settling buffer and a simple SPI-compatible serial interface with daisy-chain (DAISY) and ALARM features.

The devices operate from a single 5-V analog supply and can accommodate true bipolar input signals up to
±2.5 × VREF. The devices offer a constant 1-MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The integration of multichannel precision analog front-end circuits with high input impedance and a precision ADC operating from a single 5-V supply offers a simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits.

8.2 Functional Block Diagram

ADS8684A ADS8688A fbd_ads8688A_sbas680.gif

8.3 Feature Description

8.3.1 Analog Inputs

The ADS8684A and ADS8688A have either four or eight analog input channels, respectively, such that the positive inputs AIN_nP (n = 0 to 3 or 7) are the single-ended analog inputs and the negative inputs AIN_nGND are tied to GND. Figure 67 shows the simplified circuit schematic for each analog input channel, including the input overvoltage protection circuit, PGA, low-pass filter (LPF), high-speed ADC driver, and analog multiplexer.

ADS8684A ADS8688A an_input_channel_sbas582.gif
NOTE: n = 0 to 3 for the ADS8684A and n = 0 to 7 for the ADS8688A.
Figure 67. Front-End Circuit Schematic for Each Analog Input Channel

The devices can support multiple unipolar or bipolar, single-ended input voltage ranges based on the configuration of the program registers. As explained in the Range Select Registers section, the input voltage range for each analog channel can be configured to bipolar ±2.5 × VREF, ±1.25 × VREF, ±0.625 × VREF, ±0.3125 × VREF, and ±0.15625 × VREF or unipolar 0 to 2.5 × VREF, 0 to 1.25 × VREF, 0 to 0.625 × VREF, and 0 to 0.3125 × VREF. With the internal or external reference voltage set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of ±10.24 V, ±5.12 V, ±2.56 V, ±1.28 V, and ±0.64 V or unipolar ranges of 0 V to 10.24 V, 0 V to 5.12 V, 0 V to 2.56 V, and 0 V to 1.28 V. Any of these input ranges can be assigned to any analog input channel of the device. For instance, the ±2.5 × VREF range can be assigned to AIN_1P, the ±1.25 × VREF range can be assigned to AIN_2P, the 0 V to 2.5 × VREF range can be assigned to AIN_3P, and so forth.

The devices sample the voltage difference (AIN_nP – AIN_nGND) between the selected analog input channel and the AIN_nGND pin. The devices allow a ±0.1-V range on the AIN_nGND pin for all analog input channels. This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_nGND pin of the device to the sensor or signal-conditioning ground is recommended.

If the analog input pins (AIN_nP) to the devices are left floating, the output of the ADC corresponds to an internal biasing voltage. The output from the ADC must be considered as invalid if the devices are operated with floating input pins. This condition does not cause any damage to the devices, which are fully functional when a valid input voltage is applied to the pins.

8.3.2 Analog Input Impedance

Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance is independent of either the ADC sampling frequency, the input signal frequency, or range. The primary advantage of such high-impedance inputs is the ease of driving the ADC inputs without requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system because this ADC does not require any high-voltage front-end drivers. In most applications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantly simplifying the design of the signal chain.

In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input pin with an equivalent resistance on the AIN_nGND pin is recommended. This matching helps to cancel any additional offset error contributed by the external resistance.

8.3.3 Input Overvoltage Protection Circuit

The ADS8684A and ADS8688A feature an internal overvoltage protection circuit on each of the four or eight analog input channels, respectively. Use these protection circuits as a secondary protection scheme to protect the device. Using external protection devices against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions is highly recommended. The conceptual block diagram of the internal overvoltage protection (OVP) circuit is shown in Figure 68.

ADS8684A ADS8688A an_ovp_clamp_sbas582.gifFigure 68. Input Overvoltage Protection Circuit Schematic

As shown in Figure 68, the combination of the 1-MΩ input resistors along with the PGA gain-setting resistors (RFB and RDC) limit the current flowing into the input pins. A combination of antiparallel diodes (D1 and D2) are added on each input pin to protect the internal circuitry and set the overvoltage protection limits.

Table 1 explains the various operating conditions for the device when the device is powered on. Table 1 indicates that when the AVDD pin of the device is connected to the proper supply voltage (AVDD = 5 V) or offers a low impedance of < 30 kΩ, the internal overvoltage protection circuit can withstand up to ±20 V on the analog input pins.

Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ(1)

INPUT CONDITION
(VOVP = ±20 V)
TEST CONDITION ADC OUTPUT COMMENTS
|VIN| < |VRANGE| Within operating range All input ranges Valid Device functions as per data sheet specifications
|VRANGE| < |VIN| < |VOVP| Beyond operating range but within overvoltage range All input ranges Saturated ADC output is saturated, but device is internally protected (not recommended for extended time)
|VIN| > |VOVP| Beyond overvoltage range All input ranges Saturated This usage condition may cause irreversible damage to the device
(1) GND = 0, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0.

The results indicated in Table 1 are based on an assumption that the analog input pins are driven by very low impedance sources (RS is approximately 0). However, if the sources driving the inputs have higher impedance, the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Note that higher source impedance results in gain errors and contributes to overall system noise performance.

Figure 69 shows the voltage versus current response of the internal overvoltage protection circuit when the device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pins is limited by the 1-MΩ input impedance. However, for voltages beyond ±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.

The same overvoltage protection circuit also provides protection to the device when the device is not powered on and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 2.

Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ(1)

INPUT CONDITION
(VOVP = ±11 V)
TEST CONDITION ADC OUTPUT COMMENTS
|VIN| < |VOVP| Within overvoltage range All input ranges Invalid Device is not functional but is protected internally by the OVP circuit.
|VIN| > |VOVP| Beyond overvoltage range All input ranges Invalid This usage condition may cause irreversible damage to the device.
(1) AVDD = floating, GND = 0, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0.

Figure 70 shows the voltage versus current response of the internal overvoltage protection circuit when the device is not powered on. According to this I-V response, the current flowing into the device input pins is limited by the 1-MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.

ADS8684A ADS8688A C003_SBAS492.pngFigure 69. I-V Curve for an Input OVP Circuit
ADS8684A ADS8688A C004_SBAS582.pngFigure 70. I-V Curve for an Input OVP Circuit
(AVDD = Floating)

8.3.4 Programmable Gain Amplifier (PGA)

The devices offer a programmable gain amplifier (PGA) at each individual analog input channel, which converts the original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly adjusted by setting the Range_CHn[3:0] (n = 0 to 3 or 7) bits in the program register. The default or power-on state for the Range_CHn[3:0] bits is 0000, which corresponds to an input signal range of ±2.5 × VREF. Table 3 lists the various configurations of the Range_CHn[3:0] bits for the different analog input voltage ranges.

The PGA uses a very highly-matched network of resistors for multiple gain configurations. Matching between these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low across all channels and input ranges.

Table 3. Input Range Selection Bits Configuration

ANALOG INPUT RANGE Range_CHn[3:0]
BIT 3 BIT 2 BIT 1 BIT 0
±2.5 × VREF 0 0 0 0
±1.25 × VREF 0 0 0 1
±0.625 × VREF 0 0 1 0
±0.3125 × VREF 0 0 1 1
±0.15625 × VREF 1 0 1 1
0 to 2.5 × VREF 0 1 0 1
0 to 1.25 × VREF 0 1 1 0
0 to 0.625 × VREF 0 1 1 1
0 to 0.3125 × VREF 1 1 1 1

8.3.5 Second-Order, Low-Pass Filter (LPF)

In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel of the ADS8684A and ADS8688A features a second-order, antialiasing LPF at the output of the PGA. The magnitude and phase response of the analog antialiasing filter are shown in Figure 71 and Figure 72, respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to
15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC.

ADS8684A ADS8688A C064_SBAS680.png
Figure 71. Second-Order LPF Magnitude Response
ADS8684A ADS8688A C065_SBAS680.png
Figure 72. Second-Order LPF Phase Response

8.3.6 ADC Driver

In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog input channel of the device. During transition from one channel of the multiplexer to another channel, the fast integrated driver ensures that the multiplexer output settles to a 16-bit accuracy within the acquisition time of the ADC, irrespective of the input levels on the respective channels.

8.3.7 Multiplexer (MUX)

The ADS8684A and ADS8688A feature an integrated 4- and 8-channel analog multiplexer, respectively. For each analog input channel, the voltage difference between the positive analog input AIN_nP and the negative ground input AIN_nGND is conditioned by the analog front-end circuitry before being fed into the multiplexer. The output of the multiplexer is directly sampled by the ADC. The multiplexer in the device can scan these analog inputs in either manual or auto-scan mode, as explained in the Channel Sequencing Modes section. In manual mode (MAN_Ch_n), the channel is selected for every sample via a register write; in auto-scan mode (AUTO_RST), the channel number is incremented automatically on every CS falling edge after the present channel is sampled. The analog inputs can be selected for an auto scan with register settings (see the Auto-Scan Sequencing Control Registers section). The devices automatically scan only the selected analog inputs in ascending order.

The maximum overall throughput for the ADS8684A and ADS8688A is specified at 500 kSPS across all channels. The per channel throughput is dependent on the number of channels selected in the multiplexer scanning sequence. For example, the throughput per channel is equal to 250 kSPS if only two channels are selected, but is equal to 125 kSPS per channel if four channels are selected (as in the ADS8684A), and so forth.

See Table 6 for command register settings to switch between the auto-scan mode and manual mode for individual analog channels.

8.3.8 Reference

The ADS8684A and ADS8688A can operate with either an internal voltage reference or an external voltage reference using the internal buffer. The internal or external reference selection is determined by an external REFSEL pin. The devices have a built-in buffer amplifier to drive the actual reference input of the internal ADC core for maximizing performance.

8.3.8.1 Internal Reference

The devices have an internal 4.096-V (nominal value) reference. In order to select the internal reference, the REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5) becomes an output pin with the internal reference value. Placing a 10-µF (minimum) decoupling capacitor between the REFIO pin and REFGND (pin 6) is recommended, as shown in Figure 73. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such as the OPA320).

ADS8684A ADS8688A an_reference_int_sbas582.gifFigure 73. Device Connections for Using an Internal 4.096-V Reference

The device internal reference is trimmed to a maximum initial accuracy of ±1 mV. The histogram in Figure 74 shows the distribution of the internal voltage reference output taken from more than 3300 production devices.

ADS8684A ADS8688A C064_SBAS582.pngFigure 74. Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device itself.

In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer's suggested reflow profile, as explained in application report SNOA550. The internal voltage reference output is measured before and after the reflow process and the typical shift in value is shown in Figure 75. Although all tested units exhibit a positive shift in their output voltages, negative shifts are also possible. Note that the histogram in Figure 75 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8684A and ADS8688A in the second pass to minimize device exposure to thermal stress.

ADS8684A ADS8688A C065_SBAS582.pngFigure 75. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to 125°C. Figure 76 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the reference voltage drift over temperature is 6 ppm/°C (Figure 77) and the maximum specified temperature drift is equal to 10 ppm/°C.

ADS8684A ADS8688A C053_SBAS582.png
Figure 76. Variation of the Internal Reference Output (REFIO) Across Supply and Temperature
ADS8684A ADS8688A C054_SBAS582.png
AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C
Figure 77. Internal Reference Temperature Drift Histogram

8.3.8.2 External Reference

For applications that require a better reference voltage or a common reference voltage for multiple devices, the ADS8684A and ADS8688A offer a provision to use an external reference along with an internal buffer to drive the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin high or connect this pin to the DVDD supply. In this mode, an external 4.096-V reference must be applied at REFIO (pin 5), which becomes an input pin. Any low-power, low-drift, or small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin, which is internally connected to the ADC reference input. The output of the external reference must be appropriately filtered to minimize the resulting effect of the reference noise on system performance. A typical connection diagram for this mode is shown in Figure 78.

ADS8684A ADS8688A an_reference_ext_sbas582.gifFigure 78. Device Connections for Using an External 4.096-V Reference

The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must be placed between REFCAP (pin 7) and REFGND (pin 6). Place another capacitor of 1 µF as close to the REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac or dc loads because of the limited current output capability of this buffer.

The performance of the internal buffer output is very stable across the entire operating temperature range of –40°C to 125°C. Figure 79 shows the variation in the REFCAP output across temperature for different values of the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 1 ppm/°C (Figure 80) and the maximum specified temperature drift is equal to 1.5 ppm/°C.

ADS8684A ADS8688A C055_SBAS582.png
Figure 79. Variation of the Reference Buffer Output (REFCAP) vs Supply and Temperature
ADS8684A ADS8688A C056_SBAS582.png
AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C
Figure 80. Reference Buffer Temperature Drift Histogram

8.3.9 Auxiliary Channel

The devices include a single-ended auxiliary input channel (AUX_IN and AUX_GND). The AUX channel provides direct interface to an internal, high-precision, 16-bit ADC through the multiplexer because this channel does not include the front-end analog signal conditioning that the other analog input channels have. The AUX channel supports a single unipolar input range of 0 V to VREF because there is no front-end PGA. The input signal on the AUX_IN pin can vary from 0 V to VREF, whereas the AUX_GND pin must be tied to GND.

When a conversion is initiated, the voltage between these pins is sampled directly on an internal sampling capacitor (75 pF, typical). The input current required to charge the sampling capacitor is determined by several factors, including the sampling rate, input frequency, and source impedance. For slow applications that use a low-impedance source, the inputs of the AUX channel can be directly driven. When the throughput, input frequency, or the source impedance increases, a driving amplifier must be used at the input to achieve good ac performance from the AUX channel. Some key requirements of the driving amplifier are discussed in the Input Driver for the AUX Channel section.

The AUX channel in the ADS8684A and ADS8688A offers a true 16-bit performance with no missing codes. Some typical performance characteristics of the AUX channel are shown in Figure 81 to Figure 84.

ADS8684A ADS8688A C066_SBAS680.png
Mean = 32767.15, sigma = 0.83
Figure 81. DC Histogram for Mid-Scale Input
(AUX Channel)
ADS8684A ADS8688A C068_SBAS680.png
fIN = 1 kHz, SNR = 88.2 dB, SINAD = 88.1 dB, THD = –102 dB, SFDR = 102 dB, number of points = 64k
Figure 83. Typical FFT Plot
(AUX Channel)
ADS8684A ADS8688A C067_SBAS680.png
AUX channel
Figure 82. Offset and Gain vs Temperature
(AUX Channel)
ADS8684A ADS8688A C069_SBAS680.png
fIN = 1 kHz
Figure 84. SNR, SINAD, and THD vs Temperature
(AUX Channel)

8.3.9.1 Input Driver for the AUX Channel

For applications that use the AUX input channels at high throughput and high input frequency, a driving amplifier with low output impedance is required to meet the ac performance of the internal 16-bit ADC. Some key specifications of the input driving amplifier are discussed below:

  • Small-signal bandwidth. The small-signal bandwidth of the input driving amplifier must be much higher than the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the bandwidth limitation of the amplifier. In a typical data acquisition system, a low cut-off frequency, antialiasing filter is used at the inputs of a high-resolution ADC. The amplifier driving the antialiasing filter must have a low closed-loop output impedance for stability, thus implying a higher gain bandwidth for the amplifier. Higher small-signal bandwidth also minimizes the harmonic distortion at higher input frequencies. In general, the amplifier bandwidth requirements can be calculated on the basis of Equation 1.
  • Equation 1. ADS8684A ADS8688A aux_eqn_gbw.gif

    where

    • f–3dB is the 3-dB bandwidth of the RC filter.
  • Distortion. In order to achieve the distortion performance of the AUX channel, the distortion of the input driver must be at least 10 dB lower than the specified distortion of the internal ADC, as shown in Equation 2.
  • Equation 2. ADS8684A ADS8688A aux_eqn_thd.gif
  • Noise. Careful considerations must be made to select a low-noise, front-end amplifier in order to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by the low cut-off frequency of the input antialiasing filter, as explained in Equation 3.
  • Equation 3. ADS8684A ADS8688A aux_eqn_noise.gif

    where

    • V1 / f_AMP_PP is the peak-to-peak flicker noise,
    • en_RMS is the amplifier broadband noise density in nV/√Hz, and
    • NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.

8.3.10 ADC Transfer Function

The ADS8684A and ADS8688A are a family of multichannel devices that support single-ended, bipolar, and unipolar input ranges on all input channels. The output of the devices is in straight binary format for both bipolar and unipolar input ranges. The format for the output codes is the same across all analog channels.

The ideal transfer characteristic for each ADC channel for all input ranges is shown in Figure 85. The full-scale range (FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and the negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 216 = FSR / 65536 because the resolution of the ADC is 16 bits. For a reference voltage of VREF = 4.096 V, the LSB values corresponding to the different input ranges are listed in Table 4.

ADS8684A ADS8688A an_adc_tx_function_sbas582.gifFigure 85. 16-Bit ADC Transfer Function (Straight-Binary Format)

Table 4. ADC LSB Values for Different Input Ranges (VREF = 4.096 V)

INPUT RANGE POSITIVE FULL-SCALE NEGATIVE FULL-SCALE FULL-SCALE RANGE LSB (µV)
±2.5 × VREF 10.24 V –10.24 V 20.48 V 312.50
±1.25 × VREF 5.12 V –5.12 V 10.24 V 156.25
±0.625 × VREF 2.56 V –2.56 V 5.12 V 78.125
±0.3125 × VREF 1.28 V –1.28 V 2.56 V 39.0625
±0.15625 × VREF 0.64 V –0.64 V 1.28 V 19.53125
0 to 2.5 × VREF 10.24 V 0 V 10.24 V 156.25
0 to 1.25 × VREF 5.12 V 0 V 5.12 V 78.125
0 to 0.625 × VREF 2.56 V 0 V 2.56 V 39.0625
0 to 0.3125 × VREF 1.28 V 0 V 1.28 V 19.53125

8.3.11 Alarm Feature

The devices have an active-high ALARM output on pin 35. The ALARM signal is synchronous and changes its state on the 16th falling edge of the SCLK signal. A high level on ALARM indicates that the alarm flag has tripped on one or more channels of the device. This pin can be wired to interrupt the host input. When an ALARM interrupt is received, the alarm flag registers are read to determine which channels have an alarm. The devices feature independently-programmable alarms for each channel. There are two alarms per channel (a low and a high alarm) and each alarm threshold has a separate hysteresis setting.

The ADS8684A and ADS8688A set a high alarm when the digital output for a particular channel exceeds the high alarm upper limit [high alarm threshold (T) + hysteresis (H)]. The alarm resets when the digital output for the channel is less than or equal to the high alarm lower limit (high alarm T – H – 2). This function is shown in Figure 86.

Similarly, the lower alarm is triggered when the digital output for a particular channel falls below the low alarm lower limit (low alarm threshold T – H – 1). The alarm resets when the digital output for the channel is greater than or equal to the low alarm higher limit (low alarm T + H + 1). This function is shown in Figure 87.

ADS8684A ADS8688A an_alarm_hyst_high_sbas582.gifFigure 86. High-ALARM Hysteresis
ADS8684A ADS8688A an_alarm_hyst_low_sbas582.gifFigure 87. Low-ALARM Hysteresis

Figure 88 shows a functional block diagram for a single-channel alarm. There are two flags for each high and low alarm: active alarm flag and tripped alarm flag; see the Alarm Flag Registers (Read-Only) section for more details. The active alarm flag is triggered when an alarm condition is encountered for a particular channel; the active alarm flag resets when the alarm shuts off. A tripped alarm flag sets an alarm condition in the same manner as for an active alarm flag. However, the tripped alarm flag remains latched and resets only when the appropriate alarm flag register is read.

ADS8684A ADS8688A an_alarm_func_sbas582.gifFigure 88. Alarm Functionality Schematic

8.4 Device Functional Modes

8.4.1 Device Interface

8.4.1.1 Digital Pin Description

The digital data interface for the ADS8684A and ADS8688A is shown in Figure 89.

ADS8684A ADS8688A devop_pin_config_sbas680.gifFigure 89. Pin Configuration for the Digital Interface

The signals shown in Figure 89 are summarized as follows:

8.4.1.1.1 CS (Input)

CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample the input signal from the selected channel and a conversion is initiated using the internal clock. The device settings for the next data frame can be input during this conversion process. When the CS signal is high, the ADC is considered to be in an idle state.

8.4.1.1.2 SCLK (Input)

This pin indicates the external clock input for the data interface. All synchronous accesses to the device are timed with respect to the falling edges of the SCLK signal.

8.4.1.1.3 SDI (Input)

SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of the CS signal.

8.4.1.1.4 SDO (Output)

SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data output frame varies depending on the register setting for the SDO format; see Table 13. A low level on CS releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z state when CS goes high.

8.4.1.1.5 DAISY (Input)

DAISY is a serial input pin. When multiple devices are connected in daisy-chain mode, as illustrated in Figure 92, the DAISY pin of the first device in the chain is connected to GND. The DAISY pin of every subsequent device is connected to the SDO output pin of the previous device, and the SDO output of the last device in the chain goes to the SDI of the host processor. If an application uses a stand-alone device, the DAISY pin is connected to GND.

8.4.1.1.6 RST/PD (Input)

RST/PD is a dual-function pin. Figure 90 shows the timing of this pin and Table 5 explains the usage of this pin.

ADS8684A ADS8688A reg_hw_pd_rst_sbas582.gifFigure 90. RST/PD Pin Timing

Table 5. RST/PD Pin Functionality

CONDITION DEVICE MODE
40 ns < tPL_RST_PD ≤ 100 ns The device is in RST mode and does not enter PWR_DN mode.
100 ns < tPL_RST_PD < 400 ns The device is in RST mode and may or may not enter PWR_DN mode.
NOTE: This setting is not recommended.
tPL_RST_PD ≥ 400 ns The device enters PWR_DN mode and the program registers are reset to default value.

The devices can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for at least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time regardless of the status of other pins (including the analog input channels). When the device is in power-down mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.

The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back to a logic high state, the devices are placed in normal mode. One valid write operation must be executed on the program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to initiate conversions.

When the RST/PD pin is pulled back to a logic high level, the devices wake-up in a default state in which the program registers are reset to their default values.

8.4.1.2 Data Acquisition Example

This section provides an example of how a host processor can use the device interface to configure the device internal registers as well as convert and acquire data for sampling a particular input channel. The timing diagram shown in Figure 91 provides further details.

ADS8684A ADS8688A devop_xface_exmpl_sbas582.gifFigure 91. Device Operation Using the Serial Interface Timing Diagram

There are four events shown in Figure 91. These events are described below:

  • Event 1: The host initiates a data conversion frame through a falling edge of the CS signal. The analog input signal at the instant of the CS falling edge is sampled by the ADC and conversion is performed using an internal oscillator clock. The analog input channel converted during this frame is selected in the previous data frame. The internal register settings of the device for the next conversion can be input during this data frame using the SDI and SCLK inputs. Initiate SCLK at this instant and latch data on the SDI line into the device on every SCLK falling edge for the next 16 SCLK cycles. At this instant, SDO goes low because the device does not output internal conversion data on the SDO line during the first 16 SCLK cycles.
  • Event 2: During the first 16 SCLK cycles, the device completes the internal conversion process and data are now ready within the converter. However, the device does not output data bits on SDO until the 16th falling edge appears on the SCLK input. Because the ADC conversion time is fixed (the maximum value is given in the Electrical Characteristics table), the 16th SCLK falling edge must appear after the internal conversion is over, otherwise data output from the device is incorrect. Therefore, the SCLK frequency cannot exceed a maximum value, as provided in the Timing Requirements: Serial Interface table.
  • Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI line. The device does not read anything from the SDI line for the remaining data frame. On the same edge, the MSB of the conversion data is output on the SDO line and can be read by the host processor on the subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is initiated.
  • Event 4: When the internal data from the device is received, the host terminates the data frame by deactivating the CS signal to high. The SDO output goes into a Hi-Z state until the next data frame is initiated, as explained in Event 1.

8.4.1.3 Host-to-Device Connection Topologies

The digital interface of the ADS8684A and ADS8688A offers a lot of flexibility in the ways that a host controller can exchange data or commands with the device. A typical connection between a host controller and a stand-alone device is illustrated in Figure 89. However, there are applications that require multiple ADCs but the host controller has limited interfacing capability. This section describes two connection topologies that can be used to address the requirements of such applications.

8.4.1.3.1 Daisy-Chain Topology

A typical connection diagram showing multiple devices in daisy-chain mode is shown in Figure 92. The CS, SCLK, and SDI inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin of the host controller, respectively. The DAISY1 input pin of the first ADC in the chain is connected to DGND, the SDO1 output pin is connected to the DAISY2 input of ADC2, and so forth. The SDON pin of the Nth ADC in the chain is connected to the SDI pin of the host controller. The devices do not require any special hardware or software configuration to enter daisy-chain mode.

ADS8684A ADS8688A daisy_schematic_sbas582.gifFigure 92. Daisy-Chain Connection Schematic

A typical timing diagram for three devices connected in daisy-chain mode is shown in Figure 93.

ADS8684A ADS8688A daisy_timing_sbas582.gifFigure 93. Three Devices Connected in Daisy-Chain Mode Timing Diagram

At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion can be entered using the SDI line that is common to all devices in the chain. During this time period, the SDO outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion result into an internal 16-bit shift register. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the digital host receives the data of ADCN, followed by the data of ADCN–1, and so forth (in MSB-first fashion). In total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain. This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. Note that the overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration.

The following points must be noted about the daisy-chain configuration illustrated in Figure 92:

  • The SDI pins for all devices are connected together so each device operates with the same internal configuration. This limitation can be overcome by spending additional host controller resources to control theCS or SDI input of devices with unique configurations.
  • If the number of devices connected in daisy-chain is more than four, loading increases on the shared output lines from the host controller (CS, SDO, and SCLK). This increased loading can lead to digital timing errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller before feeding the shared digital lines into additional devices.

8.4.1.3.2 Star Topology

A typical connection diagram showing multiple devices in the star topology is shown in Figure 94. The SDI and SCLK inputs of all devices are connected together and are controlled by a single SDO and SCLK pin of the host controller, respectively. Similarly, the SDO outputs of all devices are tied together and connected to the SDI input pin of the host controller. The CS input pin of each device is individually controlled by separate CS control lines from the host controller.

ADS8684A ADS8688A devop_star_topo_sbas582.gifFigure 94. Star Topology Connection Schematic

The timing diagram for a typical data frame in the star topology is the same as in a stand-alone device operation, as illustrated in Figure 91. The data frame for a particular device starts with the falling edge of the CS signal and ends when the CS signal goes high. Because the host controller provides separate CS control signals for each device in this topology, the user can select the devices in any order and initiate a conversion by bringing down the CS signal for that particular device. As explained in Figure 91, when CS goes high at the end of each data frame, the SDO output of the device is placed into a Hi-Z state. Therefore, the shared SDO line in the star topology is controlled only by the device with an active data frame (CS is low). In order to avoid any conflict related to multiple devices driving the SDO line at the same time, ensure that the host controller pulls down the CS signal for only one device at any particular time.

TI recommends connecting a maximum of four devices in the star topology. Beyond that, loading may increase on the shared output lines from the host controller (SDO and SCLK). This loading can lead to digital timing errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller before being fed into additional devices.

8.4.2 Device Modes

The ADS8684A and ADS8688A support multiple modes of operation that are software programmable. After powering up, the device is placed into idle mode and does not perform any function until a command is received from the user. Table 6 lists all commands to enter the different modes of the device. After power-up, the program registers wake up with the default values and require appropriate configuration settings before performing any conversion. The diagram in Figure 95 explains how to switch the device from one mode of operation to another.

ADS8684A ADS8688A devop_device_modes_sbas582.gifFigure 95. State Transition Diagram

8.4.2.1 Continued Operation in the Selected Mode (NO_OP)

Holding the SDI line low continuously (equivalent to writing a 0 to all 16 bits) during device operation continues device operation in the last selected mode (STDBY, PWR_DN, AUTO_RST, or MAN_Ch_n). In this mode, the device follows the same settings that are already configured in the program registers.

If a NO_OP condition occurs when the device is performing any read or write operation in the program register (PROG mode), then the device retains the current settings of the program registers. The device goes back to IDLE mode and waits for the user to enter a proper command to execute the program register read or write configuration.

8.4.2.2 Frame Abort Condition (FRAME_ABORT)

As explained in the Data Acquisition Example section, the device digital interface is designed such that each data frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit command word on the SDI line. The device waits to execute the command until the last bit of the command is received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If the CS signal goes high for any reason before the data transmission is complete, the device goes into an INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid data on the SDO line. The output of the ALARM pin will continue to reflect the status of input signal on the previously selected channel.

8.4.2.3 STANDBY Mode (STDBY)

The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The internal reference and buffer is not powered down, and therefore, the devices can be quickly powered up in 20 µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not reset to the default values.

To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of 8200h, as shown in Figure 96. The command is executed and the device enters STDBY mode on the next CS rising edge following this write operation. The device remains in STDBY mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode section) during the subsequent data frames. When the device operates in STDBY mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can take place normally during this mode.

ADS8684A ADS8688A reg_standby_enter_sbas582.gifFigure 96. Enter and Remain in STDBY Mode Timing Diagram

In order to exit STDBY mode a valid 16-bit write command must be executed to enter auto (AUTO_RST) or manual (MAN_CH_n) scan mode, as shown in Figure 97. The device starts exiting STDBY mode on the next CS rising edge. At the next CS falling edge, the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample. The data output for the selected channel can be read during the same data frame, as explained in Figure 91.

ADS8684A ADS8688A reg_standby_exit_sbas582.gifFigure 97. Exit STDBY Mode Timing Diagram

8.4.2.4 Power-Down Mode (PWR_DN)

The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that the program registers are reset to default values when the devices wake up from hardware power-down, but the previous settings of the program registers are retained when the devices wake up from software power-down.

To enter PWR_DN mode using software, execute a valid write operation on the command register with a software PWR_DN command of 8300h, as shown in Figure 98. The command is executed and the device enters PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode section) during the subsequent data frames. When the device operates in PWR_DN mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in PWR_DN mode. The program register read operation can take place normally during this mode.

ADS8684A ADS8688A reg_powerdown_enter_sbas582.gifFigure 98. Enter and Remain in PWR_DN Mode Timing Diagram

In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in Figure 99. The device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode (REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle to the required accuracy before valid conversion data are output for the selected input channel.

ADS8684A ADS8688A reg_powerdown_exit_sbas582.gifFigure 99. Exit PWR_DN Mode Timing Diagram

8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)

The devices can be programmed to scan the input signal on all analog channels automatically by writing a valid auto channel sequence with a reset (AUTO_RST, A000h) command in the command register, as explained in Figure 100. As shown in Figure 100, the CS signal can be pulled high immediately after the AUTO_RST command or after reading the output data of the frame. However, in order to accurately acquire and convert the input signal on the first selected channel in the next data frame, the command frame must be a complete frame of 32 SCLK cycles.

The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control register (01h to 02h) in the program register; see the Program Register Map section. In this mode, the devices continuously cycle through the selected channels in ascending order, beginning with the lowest channel and converting all channels selected in the program register. On completion of the sequence, the devices return to the lowest count channel in the program register and repeat the sequence. The input voltage range for each channel in the auto-scan sequence can be configured by setting the Range Select Registers of the program registers.

ADS8684A ADS8688A reg_autoch_enter_sbas582.gifFigure 100. Enter AUTO_RST Mode Timing Diagram

The devices remain in AUTO_RST mode if no other valid command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. If the AUTO_RST command is executed again at any time during this mode of operation, then the sequence of the scanned channels is reset. The devices return to the lowest count channel of the auto-scan sequence in the program register and repeat the sequence. The timing diagram in Figure 101 shows this behavior using an example in which channels 0 to 2 are selected in the auto sequence. For switching between AUTO_RST mode and MAN_Ch_n mode; see the Channel Sequencing Modes section.

ADS8684A ADS8688A devop_auto_scan_sbas582.gifFigure 101. Device Operation Example in AUTO_RST Mode

8.4.2.6 Manual Channel n Select (MAN_Ch_n)

The devices can be programmed to convert a particular analog input channel by operating in manual channel n scan mode (MAN_Ch_n). This programming is done by writing a valid manual channel n select command (MAN_Ch_n) in the command register, as shown in Figure 102. As shown in Figure 102, the CS signal can be pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame. However, in order to accurately acquire and convert the input signal on the next channel, the command frame must be a complete frame of 32 SCLK cycles. See Table 6 for a list of commands to select individual channels during MAN_Ch_n mode.

ADS8684A ADS8688A reg_manualch_enter_sbas582.gifFigure 102. Enter MAN_Ch_n Scan Mode Timing Diagram

The manual channel n select command (MAN_Ch_n) is executed and the devices sample the analog input on the selected channel on the CS falling edge of the next data frame following this write operation. The input voltage range for each channel in the MAN_Ch_n mode can be configured by setting the Range Select Registers in the program registers. The device continues to sample the analog input on the same channel if no other valid command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. The timing diagram in Figure 103 shows this behavior using an example in which channel 1 is selected in the manual sequencing mode. For switching between MAN_Ch_n mode and AUTO_RST mode; see the Channel Sequencing Modes section.

ADS8684A ADS8688A devop_man_scan_sbas582.gifFigure 103. Device Operation in MAN_Ch_n Mode

8.4.2.7 Channel Sequencing Modes

The devices offer two channel sequencing modes: AUTO_RST and MAN_Ch_n.

In AUTO_RST mode, the channel number automatically increments in every subsequent frame. As explained in the Auto-Scan Sequencing Control Registers section, the analog inputs can be selected for an automatic scan with a register setting. The device automatically scans only the selected analog inputs in ascending order. The unselected analog input channels can also be powered down for optimizing power consumption in this mode of operation. The auto-mode sequence can be reset at any time during an automatic scan (using the AUTO_RST command). When the reset command is received, the ongoing auto-mode sequence is reset and restarts from the lowest selected channel in the sequence.

In MAN_Ch_n mode, the same input channel is selected during every data conversion frame. The input command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6. If a particular input channel is selected during a data frame, then the analog inputs on the same channel are sampled during the next data frame. Figure 104 shows the SDI command sequence for transitions from AUTO_RST to MAN_Ch_n mode.

ADS8684A ADS8688A devop_auto_man_scan_sbas582.gifFigure 104. Transitioning from AUTO_RST to MAN_Ch_n Mode
(Channels 0 and 5 are Selected for Auto Sequence)

Figure 105 shows the SDI command sequence for transitions from MAN_Ch_n to AUTO_RST mode. Note that each SDI command is executed on the next CS falling edge. A RST command can be issued at any instant during any channel sequencing mode, after which the device is placed into a default power-up state in the next data frame.

ADS8684A ADS8688A devop_man_auto_scan_sbas582.gifFigure 105. Transitioning from MAN_Ch_n to AUTO_RST Mode
(Channels 0 and 5 are Selected for Auto Sequence)

8.4.2.8 Reset Program Registers (RST)

The devices support a hardware and software reset (RST) mode in which all program registers are reset to their default values. The devices can be put into RST mode using a hardware pin, as explained in the RST/PD (Input) section.

The device program registers can be reset to their default values during any data frame by executing a valid write operation on the command register with a RST command of 8500h, as shown in Figure 106. The device remains in RST mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames. When the device operates in RST mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in RST mode. The values of the program register can be read normally during this mode. A valid AUTO_RST or MAN_CH_n channel selection command must be executed for initiating a conversion on a particular analog channel using the default program register settings.

ADS8684A ADS8688A reg_reset_enter_sbas582.gifFigure 106. Reset Program Registers (RST) Timing Diagram

8.5 Register Maps

The internal registers of the ADS8684A and ADS8688A are categorized into two categories: command registers and program registers.

The command registers are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n), configure the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program registers to their default values.

The program registers are used to select the sequence of channels for AUTO_RST mode, select the SDO output format, control input range settings for individual channels, control the ALARM feature, reading the alarm flags, and programming the alarm thresholds for each channel.

8.5.1 Command Register Description

The command register is a 16-bit, write-only register that is used to set the operating modes of the ADS8684A and ADS8688A. The settings in this register are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n), configure the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program registers to their default values. All command settings for this register are listed in Table 6. During power-up or reset, the default content of the command register is all 0's and the device waits for a command to be written before being placed into any mode of operation. See Figure 1 for a typical timing diagram for writing a 16-bit command into the device. The device executes the command at the end of this particular data frame when the CS signal goes high.

Table 6. Command Register Map

REGISTER MSB BYTE LSB BYTE COMMAND
(Hex)
OPERATION IN NEXT FRAME
B15 B14 B13 B12 B11 B10 B9 B8 B[7:0]
Continued Operation
(NO_OP)
0 0 0 0 0 0 0 0 0000 0000 0000h Continue operation in previous mode
Standby
(STDBY)
1 0 0 0 0 0 1 0 0000 0000 8200h Device is placed into standby mode
Power Down
(PWR_DN)
1 0 0 0 0 0 1 1 0000 0000 8300h Device is powered down
Reset program registers
(RST)
1 0 0 0 0 1 0 1 0000 0000 8500h Program register is reset to default
Auto Ch. Sequence with Reset
(AUTO_RST)
1 0 1 0 0 0 0 0 0000 0000 A000h Auto mode enabled following a reset
Manual Ch 0 Selection
(MAN_Ch_0)
1 1 0 0 0 0 0 0 0000 0000 C000h Channel 0 input is selected
Manual Ch 1 Selection
(MAN_Ch_1)
1 1 0 0 0 1 0 0 0000 0000 C400h Channel 1 input is selected
Manual Ch 2 Selection
(MAN_Ch_2)
1 1 0 0 1 0 0 0 0000 0000 C800h Channel 2 input is selected
Manual Ch 3 Selection
(MAN_Ch_3)
1 1 0 0 1 1 0 0 0000 0000 CC00h Channel 3 input is selected
Manual Ch 4 Selection
(MAN_Ch_4)(1)
1 1 0 1 0 0 0 0 0000 0000 D000h Channel 4 input is selected
Manual Ch 5 Selection
(MAN_Ch_5)
1 1 0 1 0 1 0 0 0000 0000 D400h Channel 5 input is selected
Manual Ch 6 Selection
(MAN_Ch_6)
1 1 0 1 1 0 0 0 0000 0000 D800h Channel 6 input is selected
Manual Ch 7 Selection
(MAN_Ch_7)
1 1 0 1 1 1 0 0 0000 0000 DC00h Channel 7 input is selected
Manual AUX Selection
(MAN_AUX)
1 1 1 0 0 0 0 0 0000 0000 E000h AUX channel input is selected
(1) Shading indicates bits or registers not included in the 4-channel version of the device.

8.5.2 Program Register Description

The program register is a 16-bit register used to set the operating modes of the ADS8684A and ADS8688A. The settings in this register are used to select the channel sequence for AUTO_RST mode, configure the device ID in daisy-chain mode, select the SDO output format, control input range settings for individual channels, control the ALARM feature, reading the alarm flags, and programming the alarm thresholds for each channel. All program settings for this register are listed in Table 9. During power-up or reset, the different program registers in the device wake up with their default values and the device waits for a command to be written before being placed into any mode of operation.

8.5.2.1 Program Register Read/Write Operation

The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low as well. The device receives the command (see Table 7 and Table 8) through SDI where the first seven bits (bits 15-9) represent the register address and the eighth bit (bit 8) is the write or read instruction.

For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback allows verification to determine if the correct data are entered into the device. A typical timing diagram for a program register write cycle is shown in Figure 107.

Table 7. Write Cycle Command Word

PIN REGISTER ADDRESS
(Bits 15-9)
WR/RD
(Bit 8)
DATA
(Bits 7-0)
SDI ADDR[6:0] 1 DIN[7:0]
ADS8684A ADS8688A devop_sdi_wr_sbas582.gifFigure 107. Program Register Write Cycle Timing Diagram

For a read cycle, the next eight bits (bits 7-0) on SDI are don’t care bits and SDO stays low. From the 16th SCLK falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in MSB-first fashion. A typical timing diagram for a program register read cycle is shown in Figure 108.

Table 8. Read Cycle Command Word

PIN REGISTER ADDRESS
(Bits 15-9)
WR/RD
(Bit 8)
DATA
(Bits 7-0)
SDI ADDR[6:0] 0 XXXXX
SDO 0000 000 0 DOUT[7:0]
ADS8684A ADS8688A devop_sdi_rd_sbas582.gifFigure 108. Program Register Read Cycle Timing Diagram

8.5.2.2 Program Register Map

This section provides a bit-by-bit description of each program register.

Table 9. Program Register Map

REGISTER REGISTER ADDRESS BITS[15:9] DEFAULT VALUE(1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AUTO SCAN SEQUENCING CONTROL
AUTO_SEQ_EN 01h FFh CH7_EN(2) CH6_EN CH5_EN CH4_EN CH3_EN CH2_EN CH1_EN CH0_EN
Channel Power Down 02h 00h CH7_PD CH6_PD CH5_PD CH4_PD CH3_PD CH2_PD CH1_PD CH0_PD
DEVICE FEATURES SELECTION CONTROL
Feature Select 03h 00h DEV[1:0] 0 ALARM_EN0 0 SDO [2:0]
RANGE SELECT REGISTERS
Channel 0 Input Range 05h 00h 0 0 0 0 Range Select Channel 0[3:0]
Channel 1 Input Range 06h 00h 0 0 0 0 Range Select Channel 1[3:0]
Channel 2 Input Range 07h 00h 0 0 0 0 Range Select Channel 2[3:0]
Channel 3 Input Range 08h 00h 0 0 0 0 Range Select Channel 3[3:0]
Channel 4 Input Range 09h 00h 0 0 0 0 Range Select Channel 4[3:0]
Channel 5 Input Range 0Ah 00h 0 0 0 0 Range Select Channel 5[3:0]
Channel 6 Input Range 0Bh 00h 0 0 0 0 Range Select Channel 6[3:0]
Channel 7 Input Range 0Ch 00h 0 0 0 0 Range Select Channel 7[3:0]
ALARM FLAG REGISTERS (Read-Only)
ALARM Overview Tripped-Flag 10h 00h Tripped Alarm Flag Ch7 Tripped Alarm Flag Ch6 Tripped Alarm Flag Ch5 Tripped Alarm Flag Ch4 Tripped Alarm Flag Ch3 Tripped Alarm Flag Ch2 Tripped Alarm Flag Ch1 Tripped Alarm Flag Ch0
ALARM Ch 0-3 Tripped-Flag 11h 00h Tripped Alarm Flag Ch0 Low Tripped Alarm Flag Ch0 High Tripped Alarm Flag Ch1 Low Tripped Alarm Flag Ch1 High Tripped Alarm Flag Ch2 Low Tripped Alarm Flag Ch2 High Tripped Alarm Flag Ch3 Low Tripped Alarm Flag Ch3 High
ALARM Ch 0-3 Active-Flag 12h 00h Active Alarm Flag Ch0 Low Active Alarm Flag Ch0 High Active Alarm Flag Ch1 Low Active Alarm Flag Ch1 High Active Alarm Flag Ch2 Low Active Alarm Flag Ch2 High Active Alarm Flag Ch3 Low Active Alarm Flag Ch3 High
ALARM Ch 4-7 Tripped-Flag 13h 00h Tripped Alarm Flag Ch4 Low Tripped Alarm Flag Ch4 High Tripped Alarm Flag Ch5 Low Tripped Alarm Flag Ch5 High Tripped Alarm Flag Ch6 Low Tripped Alarm Flag Ch6 High Tripped Alarm Flag Ch7 Low Tripped Alarm Flag Ch7 High
ALARM Ch 4-7 Active-Flag 14h 00h Active Alarm Flag Ch4 Low Active Alarm Flag Ch4 High Active Alarm Flag Ch5 Low Active Alarm Flag Ch5 High Active Alarm Flag Ch6 Low Active Alarm Flag Ch6 High Active Alarm Flag Ch7 Low Active Alarm Flag Ch7 High
ALARM THRESHOLD REGISTERS
Ch 0 Hysteresis 15h 00h CH0_HYST[7:0]
Ch 0 High Threshold MSB 16h FFh CH0_HT[15:8]
Ch 0 High Threshold LSB 17h FFh CH0_HT[7:0]
Ch 0 Low Threshold MSB 18h 00h CH0_LT[15:8]
Ch 0 Low Threshold LSB 19h 00h CH0_LT[7:0]

See the Alarm Threshold Setting Registers for details regarding the ALARM threshold settings registers.
Ch 7 Hysteresis 38h 00h CH7_HYST[7:0]
Ch 7 High Threshold MSB 39h FFh CH7_HT[15:8]
Ch 7 High Threshold LSB 3Ah FFh CH7_HT[7:0]
Ch 7 Low Threshold MSB 3Bh 00h CH7_LT[15:8]
Ch 7 Low Threshold LSB 3Ch 00h CH7_LT[7:0]
COMMAND READ BACK (Read-Only)
Command Read Back 3Fh 00h COMMAND_WORD[7:0]
(1) All registers are reset to the default values at power-on or at device reset using the register settings method.
(2) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.

8.5.2.3 Program Register Descriptions

8.5.2.3.1 Auto-Scan Sequencing Control Registers

In AUTO_RST mode, the device automatically scans the preselected channels in ascending order with a new channel selected for every conversion. Each individual channel can be selectively included in the auto channel sequencing. For channels not selected for auto sequencing, the analog front-end circuitry can be individually powered down.

8.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)

This register selects individual channels for sequencing in AUTO_RST mode. The default value for this register is FFh, which implies that in default condition all channels are included in the auto-scan sequence. If no channels are included in the auto sequence (that is, the value for this register is 00h), then channel 0 is selected for conversion by default.

Figure 109. AUTO_SEQ_EN Register
7 6 5 4 3 2 1 0
CH7_EN(2) CH6_EN CH5_EN CH4_EN CH3_EN CH2_EN CH1_EN CH0_EN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset

Table 10. AUTO_SEQ_EN Field Descriptions

Bit Field Type Reset Description
7 CH7_EN R/W 1h Channel 7 enable.
0 = Channel 7 is not selected for sequencing in AUTO_RST mode
1 = Channel 7 is selected for sequencing in AUTO_RST mode
6 CH6_EN R/W 1h Channel 6 enable.
0 = Channel 6 is not selected for sequencing in AUTO_RST mode
1 = Channel 6 is selected for sequencing in AUTO_RST mode
5 CH5_EN R/W 1h Channel 5 enable.
0 = Channel 5 is not selected for sequencing in AUTO_RST mode
1 = Channel 5 is selected for sequencing in AUTO_RST mode
4 CH4_EN R/W 1h Channel 4 enable.
0 = Channel 4 is not selected for sequencing in AUTO_RST mode
1 = Channel 4 is selected for sequencing in AUTO_RST mode
3 CH3_EN R/W 1h Channel 3 enable.
0 = Channel 3 is not selected for sequencing in AUTO_RST mode
1 = Channel 3 is selected for sequencing in AUTO_RST mode
2 CH2_EN R/W 1h Channel 2 enable.
0 = Channel 2 is not selected for sequencing in AUTO_RST mode
1 = Channel 2 is selected for sequencing in AUTO_RST mode
1 CH1_EN R/W 1h Channel 1 enable.
0 = Channel 1 is not selected for sequencing in AUTO_RST mode
1 = Channel 1 is selected for sequencing in AUTO_RST mode
0 CH0_EN R/W 1h Channel 0 enable.
0 = Channel 0 is not selected for sequencing in AUTO_RST mode
1 = Channel 0 is selected for sequencing in AUTO_RST mode

8.5.2.3.1.2 Channel Power Down Register (address = 02h)

This register powers down individual channels that are not included for sequencing in AUTO_RST mode. The default value for this register is 00h, which implies that in default condition all channels are powered up. If all channels are powered down (that is, the value for this register is FFh), then the analog front-end circuits for all channels are powered down and the output of the ADC contains invalid data. If the device is in MAN-Ch_n mode and the selected channel is powered down, then the device yields invalid output that can also trigger a false alarm condition.

Figure 110. Channel Power Down Register
7 6 5 4 3 2 1 0
CH7_PD(2) CH6_PD CH5_PD CH4_PD CH3_PD CH2_PD CH1_PD CH0_PD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 11. Channel Power Down Register Field Descriptions

Bit Field Type Reset Description
7 CH7_PD R/W 0h Channel 7 power-down.
0 = The analog front-end on channel 7 is powered up and channel 7 can be included in the AUTO_RST sequence
1 = The analog front-end on channel 7 is powered down and channel 7 cannot be included in the AUTO_RST sequence
6 CH6_PD R/W 0h Channel 6 power-down.
0 = The analog front-end on channel 6 is powered up and channel 6 can be included in the AUTO_RST sequence
1 = The analog front-end on channel 6 is powered down and channel 6 cannot be included in the AUTO_RST sequence
5 CH5_PD R/W 0h Channel 5 power-down.
0 = The analog front-end on channel 5 is powered up and channel 5 can be included in the AUTO_RST sequence
1 = The analog front-end on channel 5 is powered down and channel 5 cannot be included in the AUTO_RST sequence
4 CH4_PD R/W 0h Channel 4 power-down.
0 = The analog front-end on channel 4 is powered up and channel 4 can be included in the AUTO_RST sequence
1 = The analog front-end on channel 4 is powered down and channel 4 cannot be included in the AUTO_RST sequence
3 CH3_PD R/W 0h Channel 3 power-down.
0 = The analog front-end on channel 3 is powered up and channel 3 can be included in the AUTO_RST sequence
1 = The analog front end on channel 3 is powered down and channel 3 cannot be included in the AUTO_RST sequence
2 CH2_PD R/W 0h Channel 2 power-down.
0 = The analog front end on channel 2 is powered up and channel 2 can be included in the AUTO_RST sequence
1 = The analog front end on channel 2 is powered down and channel 2 cannot be included in the AUTO_RST sequence
1 CH1_PD R/W 0h Channel 1 power-down.
0 = The analog front end on channel 1 is powered up and channel 1 can be included in the AUTO_RST sequence
1 = The analog front end on channel 1 is powered down and channel 1 cannot be included in the AUTO_RST sequence
0 CH0_PD R/W 0h Channel 0 power-down.
0 = The analog front end on channel 0 is powered up and channel 0 can be included in the AUTO_RST sequence
1 = The analog front end on channel 0 is powered down and channel 0 cannot be included in the AUTO_RST sequence

8.5.2.3.2 Device Features Selection Control Register (address = 03h)

The bits in this register can be used to configure the device ID for daisy-chain operation, enable the ALARM feature, and configure the output bit format on SDO.

Figure 111. Feature Select Register
7 6 5 4 3 2 1 0
DEV[1:0] 0 ALARM_EN 0 SDO[2:0]
R/W-0h R-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Feature Select Register Field Descriptions

Bit Field Type Reset Description
7-6 DEV[1:0] R/W 0h Device ID bits.
00 = ID for device 0 in daisy-chain mode
01 = ID for device 1 in daisy-chain mode
10 = ID for device 2 in daisy-chain mode
11 = ID for device 3 in daisy-chain mode
5 0 R 0h Must always be set to 0
4 0 R/W 0h ALARM feature enable.
0 = ALARM feature is disabled
1 = ALARM feature is enabled
3 0 R 0h Must always be set to 0
2-0 SDO[2:0] R/W 0h SDO data format bits (see Table 13).

Table 13. Description of Program Register Bits for SDO Data Format

SDO FORMAT
SDO[2:0]
BEGINNING OF THE OUTPUT BIT STREAM OUTPUT FORMAT
BITS 24-9 BITS 8-5 BITS 4-3 BITS 2-0
000 16th SCLK falling edge,
no latency
Conversion result for selected channel (MSB-first) SDO pulled low
001 16th SCLK falling edge,
no latency
Conversion result for selected channel (MSB-first) Channel address(1) SDO pulled low
010 16th SCLK falling edge,
no latency
Conversion result for selected channel (MSB-first) Channel address(1) Device address(1) SDO pulled low
011 16th SCLK falling edge,
no latency
Conversion result for selected channel (MSB-first) Channel address(1) Device address(1) Input range(1)
(1) Table 14 lists the bit descriptions for these channel addresses, device addresses, and input range.

Table 14. Bit Description for the SDO Data

BIT BIT DESCRIPTION
24-9 16 bits of conversion result for the channel represented in MSB-first format.
8-5 Four bits of channel address.
0000 = Channel 0
0001 = Channel 1
0010 = Channel 2
0011 = Channel 3
0100 = Channel 4 (valid only for the ADS8688A)
0101 = Channel 5 (valid only for the ADS8688A)
0110 = Channel 6 (valid only for the ADS8688A)
0111 = Channel 7 (valid only for the ADS8688A)
4-3 Two bits of device address (mainly useful in daisy-chain mode).
2-0 Three LSB bits of input voltage range (see the Range Select Registers section).

8.5.2.3.3 Range Select Registers (addresses 05h-0Ch)

Address 05h corresponds to channel 0, address 06h corresponds to channel 1, address 07h corresponds to channel 2, address 08h corresponds to channel 3, address 09h corresponds to channel 4, address 0Ah corresponds to channel 5, address 0Bh corresponds to channel 6, and address 0Ch corresponds to channel 7.

These registers allow the selection of input ranges for all individual channels (n = 0 to 3 for the ADS8684A and n = 0 to 7 for the ADS8688A). The default value for these registers is 00h.

Figure 112. Channel n Input Range Registers
7 6 5 4 3 2 1 0
0 0 0 0 Range_CHn[3:0]
R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Channel n Input Range Registers Field Descriptions

Bit Field Type Reset Description
7-4 0 R 0h Must always be set to 0
3-0 Range_CHn[3:0] R/W 0h Input range selection bits for channel n (n = 0 to 3 for the ADS8684A and
n = 0 to 7 for the ADS8688A).
0000 = Input range is set to ±2.5 x VREF
0001 = Input range is set to ±1.25 x VREF
0010 = Input range is set to ±0.625 x VREF
0011 = Input range is set to ±0.3125 x VREF
1011 = Input range is set to ±0.15625 x VREF

0101 = Input range is set to 0 to 2.5 x VREF
0110 = Input range is set to 0 to 1.25 x VREF
0111 = Input range is set to 0 to 0.625 x VREF
1111 = Input range is set to 0 to 0.3125 x VREF

8.5.2.3.4 Alarm Flag Registers (Read-Only)

The alarm conditions related to individual channels are stored in these registers. The flags can be read when an alarm interrupt is received on the ALARM pin. There are two types of flag for every alarm: active and tripped. The active flag is set to 1 under the alarm condition (when data cross the alarm limit) and remains so as long as the alarm condition persists. The tripped flag turns on the alarm condition similar to the active flag, but remains set until read. This feature relieves the device from having to track alarms.

8.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)

The ALARM overview tripper-flags register contains the logical OR of high or low tripped alarm flags for all eight channels.

Figure 113. ALARM Overview Tripped-Flag Register
7 6 5 4 3 2 1 0
Tripped Alarm Flag Ch7(2) Tripped Alarm Flag Ch6 Tripped Alarm Flag Ch5 Tripped Alarm Flag Ch4 Tripped Alarm Flag Ch3 Tripped Alarm Flag Ch2 Tripped Alarm Flag Ch1 Tripped Alarm Flag Ch0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset

Table 16. ALARM Overview Tripped-Flag Register Field Descriptions

Bit Field Type Reset Description
7 Tripped Alarm Flag Ch7 R 0h Tripped alarm flag for all analog channels at a glance.
Each individual bit indicates a tripped alarm flag status for each channel, as per the alarm flags register for channels 7 to 0, respectively.
0 = No alarm detected
1 = Alarm detected
6 Tripped Alarm Flag Ch6 R 0h
5 Tripped Alarm Flag Ch5 R 0h
4 Tripped Alarm Flag Ch4 R 0h
3 Tripped Alarm Flag Ch3 R 0h
2 Tripped Alarm Flag Ch2 R 0h
1 Tripped Alarm Flag Ch1 R 0h
0 Tripped Alarm Flag Ch0 R 0h

8.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)

There are two alarm thresholds (high and low) per channel, with two flags for each threshold. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but remains latched until read. Registers 11h to 14h in the program registers store the active and tripped alarm flags for all individual eight channels.

Figure 114. ALARM Ch0-3 Tripped-Flag Register (address = 11h)
7 6 5 4 3 2 1 0
Tripped Alarm Flag Ch0 Low Tripped Alarm Flag Ch0 High Tripped Alarm Flag Ch1 Low Tripped Alarm Flag Ch1 High Tripped Alarm Flag Ch2 Low Tripped Alarm Flag Ch2 High Tripped Alarm Flag Ch3 Low Tripped Alarm Flag Ch3 High
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset

Table 17. ALARM Ch0-3 Tripped-Flag Register Field Descriptions

Bit Field Type Reset Description
7-0 Tripped Alarm Flag Ch n Low or High (n = 0 to 3) R 0h Tripped alarm flag high, low for channel n (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
Figure 115. ALARM Ch0-3 Active-Flag Register (address = 12h)
7 6 5 4 3 2 1 0
Active Alarm Flag Ch0 Low Active Alarm Flag Ch0 High Active Alarm Flag Ch1 Low Active Alarm Flag Ch1 High Active Alarm Flag Ch2 Low Active Alarm Flag Ch2 High Active Alarm Flag Ch3 Low Active Alarm Flag Ch3 High
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset

Table 18. ALARM Ch0-3 Active-Flag Register Field Descriptions

Bit Field Type Reset Description
7-0 Active Alarm Flag Ch n Low or High (n = 0 to 3) R 0h Active alarm flag high, low for channel n (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
Figure 116. ALARM Ch4-7 Tripped-Flag Register (address = 13h)(1)
7 6 5 4 3 2 1 0
Tripped Alarm Flag Ch4 Low Tripped Alarm Flag Ch4 High Tripped Alarm Flag Ch5 Low Tripped Alarm Flag Ch5 High Tripped Alarm Flag Ch6 Low Tripped Alarm Flag Ch6 High Tripped Alarm Flag Ch7 Low Tripped Alarm Flag Ch7 High
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset

Table 19. ALARM Ch4-7 Tripped-Flag Register Field Descriptions

Bit Field Type Reset Description
7-0 Tripped Alarm Flag Ch n Low or High (n = 4 to 7) R 0h Tripped alarm flag high, low for channel n (n = 4 to 7).
Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
(1) This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A read operation on this register outputs all 1's on the SDO line.
Figure 117. ALARM Ch4-7 Active-Flag Register (address = 14h)(1)
7 6 5 4 3 2 1 0
Active Alarm Flag Ch4 Low Active Alarm Flag Ch4 High Active Alarm Flag Ch5 Low Active Alarm Flag Ch5 High Active Alarm Flag Ch6 Low Active Alarm Flag Ch6 High Active Alarm Flag Ch7 Low Active Alarm Flag Ch7 High
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset

Table 20. ALARM Ch4-7 Active-Flag Register Field Descriptions

Bit Field Type Reset Description
7-0 Active Alarm Flag Ch n Low or High (n = 4 to 7) R 0h Active alarm flag high, low for channel n (n = 4 to 7).
Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected

8.5.2.3.5 Alarm Threshold Setting Registers

The ADS8684A and ADS8688A feature individual high and low alarm threshold settings for each channel. Each alarm threshold is 16 bits wide with 8-bit hysteresis, which is the same for both high and low threshold settings. This 40-bit setting is accomplished through five 8-bit registers associated with every high and low alarm.

NAME ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Ch 0 Hysteresis 15h CH0_HYST[7:0]
Ch 0 High Threshold MSB 16h CH0_HT[15:8]
Ch 0 High Threshold LSB 17h CH0_HT[7:0]
Ch 0 Low Threshold MSB 18h CH0_LT[15:8]
Ch 0 Low Threshold LSB 19h CH0_LT[7:0]
Ch 1 Hysteresis 1Ah CH1_HYST[7:0]
Ch 1 High Threshold MSB 1Bh CH1_HT[15:8]
Ch 1 High Threshold LSB 1Ch CH1_HT[7:0]
Ch 1 Low Threshold MSB 1Dh CH1_LT[15:8]
Ch 1 Low Threshold LSB 1Eh CH1_LT[7:0]
Ch 2 Hysteresis 1Fh CH2_HYST[7:0]
Ch 2 High Threshold MSB 20h CH2_HT[15:8]
Ch 2 High Threshold LSB 21h CH2_HT[7:0]
Ch 2 Low Threshold MSB 22h CH2_LT[15:8]
Ch 2 Low Threshold LSB 23h CH2_LT[7:0]
Ch 3 Hysteresis 24h CH3_HYST[7:0]
Ch 3 High Threshold MSB 25h CH3_HT[15:8]
Ch 3 High Threshold LSB 26h CH3_HT[7:0]
Ch 3 Low Threshold MSB 27h CH3_LT[15:8]
Ch 3 Low Threshold LSB 28h CH3_LT[7:0]
Ch 4 Hysteresis(1) 29h CH4_HYST[7:0]
Ch 4 High Threshold MSB 2Ah CH4_HT[15:8]
Ch 4 High Threshold LSB 2Bh CH4_HT[7:0]
Ch 4 Low Threshold MSB 2Ch CH4_LT[15:8]
Ch 4 Low Threshold LSB 2Dh CH4_LT[7:0]
Ch 5 Hysteresis 2Eh CH5_HYST[7:0]
Ch 5 High Threshold MSB 2Fh CH5_HT[15:8]
Ch 5 High Threshold LSB 30h CH5_HT[7:0]
Ch 5 Low Threshold MSB 31h CH5_LT[15:8]
Ch 5 Low Threshold LSB 32h CH5_LT[7:0]
Ch 6 Hysteresis 33h CH6_HYST[7:0]
Ch 6 High Threshold MSB 34h CH6_HT[15:8]
Ch 6 High Threshold LSB 35h CH6_HT[7:0]
Ch 6 Low Threshold MSB 36h CH6_LT[15:8]
Ch 6 Low Threshold LSB 37h CH6_LT[7:0]
Ch 7 Hysteresis 38h CH7_HYST[7:0]
Ch 7 High Threshold MSB 39h CH7_HT[15:8]
Ch 7 High Threshold LSB 3Ah CH7_HT[7:0]
Ch 7 Low Threshold MSB 3Bh CH7_LT[15:8]
Ch 7 Low Threshold LSB 3Ch CH7_LT[7:0]
Figure 118. Ch n Hysteresis Registers
7 6 5 4 3 2 1 0
CHn_HYST[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. Channel n Hysteresis Register Field Descriptions
(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit Field Type Reset Description
7-0 Channel n Hysteresis[7-0]
(n = 0 to 7 for the ADS8688A;
n = 0 to 3 for the ADS8684A)
R/W 0h These bits set the channel high and low alarm hysteresis for channel n(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)
For example, bits 7-0 of the channel 0 register (address 15h) set the channel 0 alarm hysteresis.

00000000 = No hysteresis

00000001 = ±1-LSB hysteresis

00000010 to 11111110 = ±2-LSB to ±254-LSB hysteresis

11111111 = ±255-LSB hysteresis

Figure 119. Ch n High Threshold MSB Registers
7 6 5 4 3 2 1 0
CHn_HT[15:8]
R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset

Table 22. Channel n High Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit Field Type Reset Description
7-0 CHn_HT[15:8]
(n = 0 to 7 for the ADS8688A;
n = 0 to 3 for the ADS8684A)
R/W 1h These bits set the MSB byte for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 16h) set the MSB byte for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the ch 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the ch 0 high threshold LSB register (address 17h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 120. Ch n High Threshold LSB Registers
7 6 5 4 3 2 1 0
CHn_HT[7:0]
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. Channel n High Threshold LSB Register Field Descriptions
(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit Field Type Reset Description
7-0 CHn_HT[7-0]
(n = 0 to 7 for the ADS8688A;
n = 0 to 3 for the ADS8684A)
R/W 1h These bits set the LSB for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 17h) set the LSB for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the ch 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the ch 0 high threshold LSB register (address 17h) are set to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1111 1110 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh

Figure 121. Ch n Low Threshold MSB Registers
7 6 5 4 3 2 1 0
CHn_LT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 24. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit Field Type Reset Description
7-0 CHn_LT[15:8]
(n = 0 to 7 for the ADS8688A;
n = 0 to 3 for the ADS8684A)
R/W 0h These bits set the MSB byte for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 18h) set the MSB byte for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the ch 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the ch 0 low threshold LSB register (address 19h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 122. Ch n Low Threshold LSB Registers
7 6 5 4 3 2 1 0
CHn_LT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit Field Type Reset Description
7-0 CHn_LT[7-0]
(n = 0 to 7 for the ADS8688A;
n = 0 to 3 for the ADS8684A)
R/W 0h These bits set the LSB for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 19h) set the LSB for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the ch 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the ch 0 low threshold LSB register (address 19h) are set to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1110 1111 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh

8.5.2.3.6 Command Read-Back Register (address = 3Fh)

This register allows the device mode of operation to be read. On execution of this command, the device outputs the command word executed in the previous data frame. The output of the command register appears on SDO from the 16th falling edge onwards in an MSB-first format. All information regarding the command register is contained in the first eight bits and the last eight bits are 0 (see Table 6), thus the command read-back operation can be stopped after the 24th SCLK cycle.

Figure 123. Command Read-Back Register
7 6 5 4 3 2 1 0
COMMAND_WORD[15:8]
R-0h
LEGEND: R = Read only; -n = value after reset

Table 26. Command Read-Back Register Field Descriptions

Bit Field Type Reset Description
7-0 COMMAND_WORD[15:8] R 0h Command executed in previous data frame.