ZHCSIJ3C June 2008 – July 2018
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
The design is optimized to show the input source impedance (RSOURCE) from the 100 Ω to 10000 Ω required to meet a 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xVREF (2.5 V) and 2xVREF (5 V) input ranges.