| tconv |
Conversion time |
+VBD = 1.8 V |
|
|
16 |
SCLK |
| +VBD = 3 V |
|
|
16 |
| +VBD = 5 V |
|
|
16 |
| tq |
Minimum quiet sampling time needed from bus 3-state to start of next conversion |
+VBD = 1.8 V |
40 |
|
|
ns |
| +VBD = 3 V |
40 |
|
|
| +VBD = 5 V |
40 |
|
|
| td1 |
Delay time, CS low to first data (DO–15) out |
+VBD = 1.8 V |
|
|
38 |
ns |
| +VBD = 3 V |
|
|
27 |
| +VBD = 5 V |
|
|
17 |
| tsu1 |
Setup time, CS low to first rising edge of SCLK |
+VBD = 1.8 V |
8 |
|
|
ns |
| +VBD = 3 V |
6 |
|
|
| +VBD = 5 V |
4 |
|
|
| td2 |
Delay time, SCLK falling to SDO next data bit valid |
+VBD = 1.8 V |
|
|
35 |
ns |
| +VBD = 3 V |
|
|
27 |
| +VBD = 5 V |
|
|
17 |
| th1 |
Hold time, SCLK falling to SDO data bit valid |
+VBD = 1.8 V |
7 |
|
|
ns |
| +VBD = 3 V |
5 |
|
|
| +VBD = 5 V |
3 |
|
|
| td3 |
Delay time, 16th SCLK falling edge to SDO 3-state |
+VBD = 1.8 V |
|
|
26 |
ns |
| +VBD = 3 V |
|
|
22 |
| +VBD = 5 V |
|
|
13 |
| tsu2 |
Setup time, SDI valid to rising edge of SCLK |
+VBD = 1.8 V |
2 |
|
|
ns |
| +VBD = 3 V |
3 |
|
|
| +VBD = 5 V |
4 |
|
|
| th2 |
Hold time, rising edge of SCLK to SDI valid |
+VBD = 1.8 V |
12 |
|
|
ns |
| +VBD = 3 V |
10 |
|
|
| +VBD = 5 V |
6 |
|
|
| tw1 |
Pulse duration CS high |
+VBD = 1.8 V |
20 |
|
|
ns |
| +VBD = 3 V |
20 |
|
|
| +VBD = 5 V |
20 |
|
|
| td4 |
Delay time CS high to SDO 3-state |
+VBD = 1.8 V |
|
|
24 |
ns |
| +VBD = 3 V |
|
|
21 |
| +VBD = 5 V |
|
|
12 |
| twh |
Pulse duration SCLK high |
+VBD = 1.8 V |
20 |
|
|
ns |
| +VBD = 3 V |
20 |
|
|
| +VBD = 5 V |
20 |
|
|
| twl |
Pulse duration SCLK low |
+VBD = 1.8 V |
20 |
|
|
ns |
| +VBD = 3 V |
20 |
|
|
| +VBD = 5 V |
20 |
|
|
|
Frequency SCLK |
+VBD = 1.8 V |
|
|
20 |
MHz |
| +VBD = 3 V |
|
|
20 |
| +VBD = 5 V |
|
|
20 |