ZHCSK88A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     ADS794x 方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.8 Timing Requirements

at DVDD(1) = 1.65 V to AVDD (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C, typical values at TA = 25°C
MIN NOM MAX UNIT
CONVERSION CYCLE
fSAMPLE Sample rate (throughput rate) SCLK = 34 MHz,
16 clock frame		 2 MSPS
fSAMPLE MAX = 1 / ( tCONV MAX + tACQ MIN) ADS7947 (12 bit), SCLK = 34 MHz 2.1 MSPS
ADS7948 (10 bit), SCLK = 34 MHz 2.57
ADS7949 (8 bit), SCLK = 34 MHz 3
tACQ Acquisition time 80 ns
POWER DOWN
tPDSU Setup time, PDEN high to CS rising edge
(see Figure 45 and Figure 46)		 2 ns
tPDH Hold time, CS rising edge to PDEN falling edge (see Figure 45) 20 ns
SPI INTERFACE TIMINGS
tW1 Pulse duration, CS high 25 ns
tSU1 Setup time, CS low to first rising edge of SCLK DVDD = 1.8 V 3.5 ns
DVDD = 3 V 3.5
DVDD = 5 V 3.5
tD4 Delay time, CS rising edge from conversion end
(see the tCONV specification for conversion time)		 10 ns
tWH Pulse duration, SCLK high 11 ns
tWL Pulse duration, SCLK low 11 ns
fSCLK SCLK frequency 0.4 34 40 MHz
(1) 1.8-V specifications apply from 1.65 V to 2 V; 3-V specifications apply form 2.7 V to 3.6 V; 5-V specifications apply from 4.75 V to 5.25 V.