SLAS492B September 2005 – August 2016 ADS7886
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- DCK|6
订购信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| +IN to AGND | –0.3 | VDD +0.3 | V | |
| +VDD to AGND | –0.3 | 7 | V | |
| Digital input voltage to GND | –0.3 | 7 | V | |
| Digital output to GND | –0.3 | (VDD + 0.3) | V | |
| Power dissipation, SOT-23 and SC70 packages | (TJ Max–TA)/RθJA | |||
| Lead temperature, soldering | Vapor phase (60 s) | 215 | °C | |
| Infrared (15 s) | 220 | |||
| Junction temperature (TJ Max) | 150 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| TA | Operating temperature | –40 | 125 | °C |
7.4 Thermal Information
| THERMAL METRIC(1) | ADS7886 | UNIT | ||
|---|---|---|---|---|
| DBV (SOT-23) | DCK (SC70) | |||
| 6 PINS | 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 113.4 | 149.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 54.3 | 58.9 | °C/W |
| RθJB | Junction-to-board thermal resistance | 35.3 | 41.9 | °C/W |
| ψJT | Junction-to-top characterization parameter | 4.6 | 1.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 35 | 41.3 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, f(sample) = 1 MHz (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG INPUT | ||||||
| Full-scale input voltage span(1) | 0 | VDD | V | |||
| Absolute input voltage range | +IN | –0.2 | VDD+0.2 | V | ||
| CI | Input capacitance(2) | 21 | pF | |||
| Ilkg | Input leakage current | TA = 125°C | 40 | nA | ||
| SYSTEM PERFORMANCE | ||||||
| Resolution | 12 | Bits | ||||
| No missing codes | ADS7886SB | 12 | Bits | |||
| ADS7886S | 11 | |||||
| INL | Integral nonlinearity | ADS7886SB | –1.25 | ±0.65 | 1.25 | LSB(3) |
| ADS7886S | 2 | 2 | ||||
| DNL | Differential nonlinearity | ADS7886SB | –1 | +0.4/-0.65 | 1 | LSB |
| ADS7886S | –2 | 2 | ||||
| EO | Offset error(4) | VDD = 2.35 V to 3.6 V | –2.5 | ±0.5 | 2.5 | LSB |
| VDD = 4.75 V to 5.25 V | –2 | ±0.5 | 2 | |||
| EG | Gain error | –1.75 | ±0.5 | 1.75 | LSB | |
| SAMPLING DYNAMICS | ||||||
| Conversion time | 20-MHz SCLK | 760 | 800 | ns | ||
| Acquisition time | 325 | ns | ||||
| Maximum throughput rate | 20-MHz SCLK | 1 | MHz | |||
| Aperture delay | 5 | ns | ||||
| Step Response | 160 | ns | ||||
| Overvoltage recovery | 160 | ns | ||||
| DYNAMIC CHARACTERISTICS | ||||||
| SNR | Signal-to-noise ratio | VDD = 2.35 V to 3.6 V, fI = 100 kHz | 69 | 71.25 | dB | |
| VDD = 4.75 V to 5.25 V, fI = 100 kHz | 70 | 72.25 | ||||
| SINAD | Signal-to-noise and distortion | VDD = 2.35 V to 3.6 V, fI = 100 kHz | 69 | 71.25 | dB | |
| VDD = 4.75 V to 5.25 V, fI = 100 kHz | 70 | 72.25 | ||||
| THD | Total harmonic distortion(5) | fI = 100 kHz | –84 | dB | ||
| SFDR | Spurious free dynamic range | fI = 100 kHz | 85.5 | dB | ||
| Full power bandwidth | At –3 dB | 15 | MHz | |||
| DIGITAL INPUT/OUTPUT | ||||||
| Logic family — CMOS | ||||||
| VIH | High-level input voltage | VDD = 2.35 V to 3.6 V | 1.8 | 5.25 | V | |
| VDD = 3.6 V to 5.25 V | 2.4 | 5.25 | ||||
| VIL | Low-level input voltage | VDD = 5 V | 0.8 | V | ||
| VDD = 3 V | 0.4 | |||||
| VOH | High-level output voltage | I(source) = 200 µA | VDD – 0.2 | V | ||
| VOL | Low-level output voltage | I(sink) = 200 µA | 0.4 | |||
| POWER SUPPLY REQUIREMENTS | ||||||
| +VDD | Supply voltage | 2.35 | 3.3 | 5.25 | V | |
| Supply current (normal mode) | VDD = 2.35 V to 3.6 V, 1-MHz throughput | 1.3 | 1.5 | mA | ||
| VDD = 4.75 V to 5.25 V, 1-MHz throughput | 1.5 | 2 | ||||
| VDD = 2.35 V to 3.6 V, static state | 1.1 | |||||
| VDD = 4.75 V to 5.25 V, static state | 1.5 | |||||
| Power down state supply current | SCLK off | 1 | µA | |||
| SCLK on (20 MHz) | 200 | |||||
| Power dissipation at 1-MHz throughput | VDD = 3 V | 3.9 | 4.5 | mW | ||
| VDD = 5 V | 7.5 | 10 | ||||
| Power dissipation in static state | VDD = 3 V | 3.3 | mW | |||
| VDD = 5 V | 7.5 | |||||
| Power-up time | 0.1 | µs | ||||
| Invalid conversions after power up or reset |
1 | |||||
(1) Ideal input span; does not include gain or offset error.
(2) See Figure 27 for details on the sampling circuit.
(3) LSB means least significant bit.
(4) Measured relative to an ideal full-scale input.
(5) Calculated on the first nine harmonics of the input frequency.
7.6 Timing Requirements
All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V (see Figure 1 and Figure 2) (unless otherwise specified)(1).| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tconv | Conversion time | ADS7866 | VDD = 3 V | 16 × tSCLK | ns | ||
| VDD = 5 V | 16 × tSCLK | ||||||
| tq | Minimum quiet time needed from bus 3-state to start of next conversion | VDD = 3 V | 40 | ns | |||
| VDD = 5 V | 40 | ||||||
| td1 | Delay time, CS low to first data (0) out | VDD = 3 V | 15 | 25 | ns | ||
| VDD = 5 V | 13 | 25 | |||||
| tsu1 | Setup time, CS low to SCLK low | VDD = 3 V | 10 | ns | |||
| VDD = 5 V | 10 | ||||||
| td2 | Delay time, SCLK falling to SDO | VDD = 3 V | 15 | 25 | ns | ||
| VDD = 5 V | 13 | 25 | |||||
| th1 | Hold time, SCLK falling to data valid(2) | VDD < 3 V | 7 | ns | |||
| VDD > 5 V | 5.5 | ||||||
| td3 | Delay time, 16th SCLK falling edge to SDO 3-state | VDD = 3 V | 10 | 25 | ns | ||
| VDD = 5 V | 8 | 20 | |||||
| tw1 | Pulse duration, CS | VDD = 3 V | 25 | 40 | ns | ||
| VDD = 5 V | 25 | 40 | |||||
| td4 | Delay time, CS high to SDO 3-state | VDD = 3 V | 17 | 30 | ns | ||
| VDD = 5 V | 15 | 25 | |||||
| twH | Pulse duration, SCLK high | VDD = 3 V | 0.4 × tSCLK | ns | |||
| VDD = 5 V | 0.4 × tSCLK | ||||||
| twL | Pulse duration, SCLK low | VDD = 3 V | 0.4 × tSCLK | ns | |||
| VDD = 5 V | 0.4 × tSCLK | ||||||
| Frequency, SCLK | VDD = 3 V | 20 | MHz | ||||
| VDD = 5 V | 20 | ||||||
| td5 | Delay time, second falling edge of clock and CS to enter in power down (use min spec not to accidently enter in power down) Figure 2 | VDD = 3 V | –2 | 5 | ns | ||
| VDD = 5 V | –2 | 5 | |||||
| td6 | Delay time, CS and 10th falling edge of clock to enter in power down (use max spec not to accidently enter in power down) Figure 2 | VDD = 3 V | 2 | –5 | ns | ||
| VDD = 5 V | 2 | –5 | |||||
(1) 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
(2) With 50-pf load.
Figure 1. Interface Timing Diagram
Figure 2. Entering Power Down Mode
7.7 Typical Characteristics
