ZHCSDU3A June   2015  – June 2015 ADS58J63

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: 14-Bit Burst Mode
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1  Digital Features
      2. 7.4.2  Mode 0 - Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3  Mode 2 - Decimation by 2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4  Mode 4/7 - Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5  Mode 5 - Decimation by 2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6  Mode 6 - Decimation by 4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7  Mode 8 - Burst Mode
      8. 7.4.8  Trigger Input
      9. 7.4.9  Manual Trigger Mode
      10. 7.4.10 Auto Trigger Mode
      11. 7.4.11 Over-range Indication
      12. 7.4.12 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1  Details of Serial Interface
        2. 7.5.1.2  Serial Register Write: Analog Bank
        3. 7.5.1.3  Serial Register Readout: Analog Bank
        4. 7.5.1.4  JESD Bank SPI Page Selection
        5. 7.5.1.5  Serial Register Write: Analog Bank
        6. 7.5.1.6  Serial Register Readout: Analog Bank
        7. 7.5.1.7  Digital Bank SPI Page Selection
        8. 7.5.1.8  Serial Register Write - Digital Bank
        9. 7.5.1.9  Individual Channel Programming
        10. 7.5.1.10 Serial Register Readout - Digital Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 Serdes Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Info
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1  Register 0h (offset = 0h) [reset = 0h]
        2. 7.6.3.2  Register 3h/4h (offset = 3h/4h) [reset = 0h]
        3. 7.6.3.3  Register 5h (offset = 5h) [reset = 0h]
        4. 7.6.3.4  Register 11h (offset = 11h) [reset = 0h]
        5. 7.6.3.5  Master Page (80h)
          1. 7.6.3.5.1  Register 20h (address = 20h) [reset = 0h] , Master Page (080h)
          2. 7.6.3.5.2  Register 21h (address = 21h) [reset = 0h] , Master Page (080h)
          3. 7.6.3.5.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.5.4  Register 24h (address = 24h) [reset = 0h] , Master Page (080h)
          5. 7.6.3.5.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.5.6  Register 3Ah (address = 3Ah) [reset = 0h] , Master Page (80h)
          7. 7.6.3.5.7  Register 39h (address = 39h) [reset = 0h] , Master Page (80h)
          8. 7.6.3.5.8  Register 53h (address = 53h) [reset = 0h] , Master Page (80h)
          9. 7.6.3.5.9  Register 55h (address = 55h) [reset = 0h] , Master Page (80h)
          10. 7.6.3.5.10 Register 56h (address = 56h) [reset = 0h] , Master Page (80h)
          11. 7.6.3.5.11 Register 59h (address = 59h) [reset = 0h] , Master Page (80h)
        6. 7.6.3.6  ADC Page (0Fh)
          1. 7.6.3.6.1 Register 5Fh (address = 5Fh) [reset = 0h] , ADC Page (0Fh)
          2. 7.6.3.6.2 Register 60h (address = 60h) [reset = 0h] , ADC Page (0Fh)
          3. 7.6.3.6.3 Register 60h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.6.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.6.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.6.6 Register 74h(address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.6.7 Register 75h/76h/77h/78h (address = 75h/76h/77h/78h) [reset = 0h], ADC Page (0Fh)
        7. 7.6.3.7  Interleaving Engine Page (6100h)
          1. 7.6.3.7.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.7.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        8. 7.6.3.8  Decimation Filter Page (6141h) Registers
          1. 7.6.3.8.1 Register 0h (address = 0h) [reset = 0h]
          2. 7.6.3.8.2 Register 1h (address = 1h) [reset = 0h]
          3. 7.6.3.8.3 Register 2h (address = 2h) [reset = 0h]
        9. 7.6.3.9  Main Digital Page (6800h) Registers
          1. 7.6.3.9.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.9.2 Register 42h(address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.9.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.9.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.9.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.9.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        10. 7.6.3.10 JESD Digital Page (6900h) Registers
          1. 7.6.3.10.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.10.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.10.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.10.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.10.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.10.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.10.7 Register 17h (address = 17h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.10.8 Register 19h/1Ah/1Bh/1Ch (address = 19h/1Ah/1Bh/1Ch) [reset = 0h], JESD Digital Page (6900h)
            1. 7.6.3.10.8.1 Register 1Dh/1Eh/1Fh/20h (address = 1Dh/1Eh/1Fh/20h) [reset = 0h], JESD Digital Page (6900h)
            2. 7.6.3.10.8.2 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
            3. 7.6.3.10.8.3 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        11. 7.6.3.11 JESD Analog Page (6A00h) Register
          1. 7.6.3.11.1 Register 12h/13h (address 12h/13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.11.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.11.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
      3. 8.1.3 SNR and Clock Jitter
      4. 8.1.4 ADC Test Pattern
        1. 8.1.4.1 ADC Section
        2. 8.1.4.2 Transport Layer Pattern
        3. 8.1.4.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 四通道
  • 14 位分辨率
  • 最大时钟速率：500MSPS
  • 输入带宽 (3dB)：900MHz
  • 片上抖动
  • 具有高阻抗输入的模拟输入缓冲器
  • 输出选项：
    • Rx：2 倍抽取率和 4 倍抽取率（低通滤波器）
    • 200MHz 复带宽或 100MHz 实带宽支持
    • DPD FB：突发模式，14 位输出
  • 1.9 VPP 差分满量程输入
  • JESD204B 接口：
    • 支持子类 1
    • 每个 ADC 一条信道，速率高达 10Gsps
    • 专用于通道对的 SYNC 引脚
  • 支持多芯片同步
  • 72 引脚超薄型四方扁平无引线 (VQFN) 封装 (10mm × 10mm)
  • 主要技术规格：
    • 功耗：每通道 675mW
    • 频谱性能（未抽取）
      • fIN = 190MHz 中频 (IF)（–1dBFS 时）：
        • 信噪比 (SNR)：70.4dBFS
        • 噪声频谱密度 (NSD)：–154.4dBFS/Hz
        • 无杂散动态范围 (SFDR)：86dBc（HD2，HD3），
          95dBFS（非 HD2，HD3）
      • fIN = 370 MHz IF（–3dBFS 时）：
        • SNR：68.5dBFS
        • NSD：–152.5dBFS/Hz
        • SFDR：81dBc（HD2，HD3），
          86dBFS（非 HD2，HD3）

2 应用

  • 多载波 GSM 蜂窝基础设施基站
  • 多载波多模式蜂窝基础设施基站
  • 电信接收器
  • 电信数字预失真 (DPD) 观测接收器

3 说明

ADS58J63 是一款低功耗、高带宽、14 位、500MSPS、四通道电信接收器。 ADS58J63 支持 JESD204B 串行接口，每个通道上具有 1 条信道，数据传输速率高达 10Gbps。 经缓冲的模拟输入可在较宽频率范围内提供统一输入阻抗，并最大程度地降低采样和保持毛刺脉冲能量。 ADS58J63 以超低功耗在宽输入频率范围内提供出色的无杂散动态范围 (SFDR)。 数字信号处理模块包含复混频器，后接低通滤波器。低通滤波器具有 2 倍抽取率和 4 倍抽取率两个选项，支持高达 200MHz 的接收器带宽。 此外，ADS58J63 在突发模式下还支持 14 位、500MSPS 输出，因此适用于 DPD 观测接收器。

JESD204B 接口减少了接口线路数，从而实现高系统集成度。 内部锁相环 (PLL) 会将传入的模数转换器 (ADC) 采样时钟加倍，以获得串行化各通道的 14 位数据时所使用的位时钟。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADS58J63 VQFN (72) 10.00mm x 10.00mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化框图

ADS58J63 bd_bas717.gif

4 修订历史记录

Changes from * Revision (June 2015) to A Revision

  • 已从“产品预览”更改为“量产”数据表Go