ZHCSF28B May   2016  – January 2017 ADS54J20

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1 JESD Transmitter Interface
          2. 8.4.2.5.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Information
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1 General Registers
          1. 8.5.3.1.1 Register 0h (address = 0h)
          2. 8.5.3.1.2 Register 3h (address = 3h)
          3. 8.5.3.1.3 Register 4h (address = 4h)
          4. 8.5.3.1.4 Register 5h (address = 5h)
          5. 8.5.3.1.5 Register 11h (address = 11h)
        2. 8.5.3.2 Master Page (080h) Registers
          1. 8.5.3.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.3.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.3.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.3.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.3.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.3.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.3.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.3.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.3.3 ADC Page (0Fh) Register
          1. 8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.3.4 Main Digital Page (6800h) Registers
          1. 8.5.3.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.3.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.3.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.3.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.3.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.3.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.3.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.3.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.3.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.3.5 JESD Digital Page (6900h) Registers
          1. 8.5.3.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.3.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.3.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.3.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.3.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.3.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.3.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.3.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.3.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.3.6 JESD Analog Page (6A00h) Registers
          1. 8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. 8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. 8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 12 位分辨率、双通道、1GSPS 模数转换器 (ADC)
  • 噪底：–157dBFS/Hz
  • 频谱性能（–1dBFS 时的 fIN = 170MHz）：
    • SNR：67.8dBFS
    • NSD：–155dBFS/Hz
    • 无杂散动态范围 (SFDR)：86dBc（包括交错音调）
    • SFDR：89dBc（不包括 HD2、HD3 和交错音调）
  • 频谱性能（–1dBFS 时的 fIN = 350MHz）：
    • SNR：65.6dBFS
    • NSD：–152.6dBFS/Hz
    • SFDR：75dBc
    • SFDR：85dBc（不包括 HD2、HD3 和交错音调）
  • 通道隔离：fIN = 170MHz 时为 100dBc
  • 输入满量程：1.9 VPP
  • 输入带宽 (3dB)：1.2GHz
  • 片上抖动
  • 集成宽带数字下变频器 (DDC) 模块
  • 支持 JESD204B 子类 1 接口：
    • 10.0Gbps 时每个 ADC 2 条通道
    • 5.0Gbps 时每个 ADC 4 条通道
    • 支持多芯片同步
  • 功耗：1GSPS 时为 1.35W/通道
  • 封装：72 引脚超薄型四方扁平无引线 (10mm × 10mm)

2 应用

  • 雷达和天线阵列
  • 无线宽带
  • 电缆 CMTS、DOCSIS 3.1 接收器
  • 通信测试设备
  • 微波接收器
  • 软件定义无线电 (SDR)
  • 数字转换器
  • 医疗成像和诊断功能

3 说明

ADS54J20 是一款低功耗、高带宽、12 位、1.0GSPS 双通道模数转换器 (ADC)。该器件经设计具有高 SNR，可提供 -157dBFS/Hz 的噪底，从而 协助应用在宽瞬时带宽内 实现最高动态范围。该器件支持 JESD204B 串行接口，数据传输速率高达 10Gbps，每个 ADC 可支持 2 或 4 条通道。经缓冲的模拟输入可在较宽频率范围内提供统一输入阻抗并最大程度地降低采样和保持毛刺脉冲能量。可选择将每条 ADC 通道与宽带数字下变频器 (DDC) 模块相连。ADS54J20 以超低功耗在宽输入频率范围内提供出色的无杂散动态范围 (SFDR)。

JESD204B 接口减少了接口线路数，从而实现高系统集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍，以获得对各通道的 12 位数据进行串行化所使用的位时钟。

器件信息

器件编号 封装 封装尺寸（标称值）
ADS54J20 VQFNP (72) 10.00mm x 10.00mm
  1. 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

170MHz 输入信号的快速傅立叶变换 (FFT)

ADS54J20 D000_SBAS766.gif

4 修订历史记录

Changes from A Revision (May 2016) to B Revision

  • Changed the Device Comparison TableGo
  • Added the FOVR latency parameter to the Timing Characteristics tableGo
  • Added SYSREF Not Present (Subclass 0, 2) sectionGo
  • Changed the number of clock cycles in the Fast OVR sectionGo
  • Changed the Register MapGo
  • Deleted register 39h, 3Ah, and 56h Go
  • Changed Power Supply Recommendations section Go
  • Added the Power Sequencing and Initialization sectionGo
  • Added 接收文档更新通知部分Go

Changes from * Revision (May 2016) to A Revision

  • 已发布为“量产数据”Go