ZHCSO82 November 2021 ADS130B02-Q1
PRODUCTION DATA
Table 8-10 lists the ADS130B02-Q1 registers. All register addresses not listed in Table 8-10 should be considered as reserved locations with the default setting of 0000h and the register contents should not be modified from its default setting.
ADDRESS | REGISTER | RESET VALUE | BIT 15 | BIT 14 | BIT 13 | BIT 12 | BIT 11 | BIT 10 | BIT 9 | BIT 8 |
---|---|---|---|---|---|---|---|---|---|---|
BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 | |||
DEVICE SETTINGS AND STATUS INDICATORS (Read-Only Registers) | ||||||||||
00h | ID | 52xxh | RESERVED | CHANCNT[3:0] | ||||||
RESERVED | ||||||||||
01h | STATUS | 0500h | LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
RESERVED | DRDY1 | DRDY0 | ||||||||
GLOBAL SETTINGS ACROSS CHANNELS | ||||||||||
02h | MODE | 0510h | RESERVED | REGCRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
RESERVED | TIMEOUT | RESERVED | DRDY_HiZ | RESERVED | ||||||
03h | CLOCK | 038Eh | RESERVED | CH1_EN | CH0_EN | |||||
CLK_SEL | RESERVED | OSR[2:0] | PWR[1:0] | |||||||
04h | GAIN | 0000h | RESERVED | |||||||
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | |||||||
06h | GLOBAL_CHOP_CFG | 0600h | RESERVED | GC_DLY[3:0] | GC_EN | |||||
RESERVED | ||||||||||
CHANNEL-SPECIFIC SETTINGS | ||||||||||
09h | CH0_CFG | 0000h | RESERVED | |||||||
RESERVED | MUX0[1:0] | |||||||||
0Ch | RESERVED | 8000h | RESERVED | |||||||
RESERVED | ||||||||||
0Eh | CH1_CFG | 0000h | RESERVED | |||||||
RESERVED | MUX1[1:0] | |||||||||
11h | RESERVED | 8000h | RESERVED | |||||||
RESERVED | ||||||||||
REGISTER MAP CRC REGISTER (Read-Only Register) | ||||||||||
3Eh | REGMAP_CRC | 0000h | REG_CRC[15:8] | |||||||
REG_CRC[7:0] |
Table 8-11 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
The ID register is shown in Figure 8-24 and described in Table 8-12.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHANCNT[3:0] | ||||||
R-0101b | R-0010b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-xxxxxxxxb | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0101b | Reserved Always reads 0101b |
11:8 | CHANCNT[3:0] | R | 0010b | Channel count Always reads 0010b |
7:0 | RESERVED | R | xxxxxxxxb | Reserved Values are subject to change without notice |
The STATUS register is shown in Figure 8-25 and described in Table 8-13.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-1b | R-01b | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DRDY1 | DRDY0 | |||||
R-000000b | R-0b | R-0b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R | 0b | SPI interface lock indicator 0b = Unlocked 1b = Locked |
14 | F_RESYNC | R | 0b | ADC resynchronization indicator Bit is set each time the ADC resynchronizes. 0b = No resynchronization 1b = Resynchronization occurred |
13 | REG_MAP | R | 0b | Register map CRC fault indicator 0b = No change in the register map CRC 1b = register map CRC changed |
12 | CRC_ERR | R | 0b | SPI input CRC error indicator 0b = No CRC error 1b = Input CRC error occurred |
11 | CRC_TYPE | R | 0b | CRC type indicator 0b = 16 bit CCITT 1b = 16 bit ANSI |
10 | RESET | R | 1b | Reset status indicator 0b = No reset occurred 1b = Reset occurred |
9:8 | WLENGTH[1:0] | R | 01b | Data word length indicator 00b = 16 bit 01b = 24 bits 10b = 32 bits: LSB zero padding 11b = Reserved |
7:2 | RESERVED | R | 000000b | Reserved Always reads 000000b |
1 | DRDY1 | R | 0b | Channel 1 ADC data available indicator 0b = No new data available 1b = New data available |
0 | DRDY0 | R | 0b | Channel 0 ADC data available indicator 0b = No new data available 1b = New data available |
The MODE register is shown in Figure 8-26 and described in Table 8-14.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REG_CRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-01b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | RESERVED | DRDY_HiZ | RESERVED | |||
R/W-000b | R/W-1b | R/W-00b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R/W | 00b | Reserved Always write 00b |
13 | REG_CRC_EN | R/W | 0b | Register map CRC enable 0b = Disabled 1b = Enabled |
12 | RX_CRC_EN | R/W | 0b | SPI input CRC enable 0b = Disabled 1b = Enabled |
11 | CRC_TYPE | R/W | 0b | SPI and register map CRC type selection 0b = 16 bit CCITT 1b = 16 bit ANSI |
10 | RESET | R/W | 1b | Reset Write 0b to clear this bit in the STATUS register 0b = No reset occurred 1b = Reset occurred |
9:8 | WLENGTH[1:0] | R/W | 01b | Data word length selection 00b = 16 bits 01b = 24 bits 10b = 32 bits: LSB zero padding 11b = Reserved. Do not use. |
7:5 | RESERVED | R/W | 000b | Reserved Always write 000b |
4 | TIMEOUT | R/W | 1b | SPI Timeout enable 0b = Disabled 1b = Enabled |
3:2 | RESERVED | R/W | 00b | Reserved Always write 00b |
1 | DRDY_HiZ | R/W | 0b | DRDY pin state selection when conversion data is not
available 0b = Logic high 1b = High impedance |
0 | RESERVED | R/W | 0b | Reserved Always write 0b |
The CLOCK register is shown in Figure 8-27 and described in Table 8-15.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH1_EN | CH0_EN | |||||
R-000000b | R/W-1b | R/W-1b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_SEL | RESERVED | OSR[2:0] | PWR[1:0] | ||||
R/W-1b | R/W-00b | R/W-011b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R | 000000b | Reserved Always reads 000000b |
9 | CH1_EN | R/W | 1b | Channel 1 ADC enable 0b = Disabled 1b = Enabled |
8 | CH0_EN | R/W | 1b | Channel 0 ADC enable 0b = Disabled 1b = Enabled |
7 | CLK_SEL | R/W | 1b | Clock source selection 0b = Internal oscillator 1b = External clock |
6:5 | RESERVED | R/W | 00b | Reserved Always write 00b |
4:2 | OSR[2:0] | R/W | 011b | Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 100b = 2048 101b = 4096 110b = 8192 111b = 16384 |
1:0 | PWR[1:0] | R/W | 10b | Power mode selection 00b = Very-low power 01b = Low power 10b = High resolution 11b = High resolution |
The GAIN register is shown in Figure 8-28 and described in Table 8-16.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:7 | RESERVED | R/W | 00000000 0b |
Reserved Always write 000000000b |
6:4 | PGAGAIN1[2:0] | R/W | 000b | PGA gain selection for channel 1 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
3 | RESERVED | R/W | 0b | Reserved Always write 0b |
2:0 | PGAGAIN0[2:0] | R/W | 000b | PGA gain selection for channel 0 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
The GLOBAL_CHOP_CFG register is shown in Figure 8-29 and described in Table 8-17.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GC_DLY[3:0] | GC_EN | |||||
R/W-000b | R/W-0011b | R/W-0b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | RESERVED | R/W | 000b | Reserved Always write 000b |
12:9 | GC_DLY[3:0] | R/W | 0011b | Global chop delay selection Delay in modulator clock periods (tMOD) before measurement begins. 0000b = 2 0001b = 4 0010b = 8 0011b = 16 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16484 1110b = 32768 1111b = 65536 |
8 | GC_EN | R/W | 0b | Global chop enable 0b = Disabled 1b = Enabled |
7:0 | RESERVED | R/W | 00000000b | Reserved Always write 00000000b |
The CH0_CFG register is shown in Figure 8-30 and described in Table 8-18.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | MUX0[1:0] | ||||
R/W-00b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | RESERVED | R/W | 00000000 00b | Reserved Always write 0000000000b |
5:3 | RESERVED | R | 000b | Reserved Always reads 000b |
2 | RESERVED | R/W | 0b | Reserved Always write 0b |
1:0 | MUX0[1:0] | R/W | 00b | Channel 0 input selection 00b = AIN0P and AIN0N 01b = AIN0 disconnected, ADC inputs shorted 10b = Positive dc test signal 11b = Negative dc test signal |
The CH1_CFG register is shown in Figure 8-31 and described in Table 8-19.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | MUX1[1:0] | ||||
R/W-00b | R-000b | R/W-0b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | RESERVED | R/W | 00000000 00b |
Reserved Always write 0000000000b |
5:3 | RESERVED | R | 000b | Reserved Always reads 000b |
2 | RESERVED | R/W | 0b | Reserved Always write 0b |
1:0 | MUX1[1:0] | R/W | 00b | Channel 1 input selection 00b = AIN1P and AIN1N 01b = AIN1 disconnected, ADC inputs shorted 10b = Positive dc test signal 11b = Negative dc test signal |
The REGMAP_CRC register is shown in Figure 8-32 and described in Table 8-20.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_CRC[15:8] | |||||||
R-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_CRC[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_CRC[15:0] | R | 00000000 00000000b | Register map CRC value |