ZHCSFJ3A July   2014  – September 2016 ADS1148-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Performance
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC Input and Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 8.3.2.3 Analog Input Impedance
      3. 8.3.3  Clock Source
      4. 8.3.4  Modulator
      5. 8.3.5  Digital Filter
      6. 8.3.6  Voltage Reference Input
      7. 8.3.7  Internal Voltage Reference
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Sensor Detection
      10. 8.3.10 Bias Voltage Generation
      11. 8.3.11 General-Purpose Digital I/O
      12. 8.3.12 System Monitor
        1. 8.3.12.1 Power-Supply Monitor
        2. 8.3.12.2 External Voltage Reference Monitor
        3. 8.3.12.3 Ambient Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Up
      2. 8.4.2 Reset
      3. 8.4.3 Power-Down Mode
      4. 8.4.4 Conversion Control
        1. 8.4.4.1 Settling Time for Channel Multiplexing
        2. 8.4.4.2 Channel Cycling and Overload Recovery
        3. 8.4.4.3 Single-Cycle Settling
        4. 8.4.4.4 Digital Filter Reset Operation
      5. 8.4.5 Calibration
        1. 8.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 8.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 8.4.5.3 Calibration Commands
          1. 8.4.5.3.1 System Offset and Self Offset Calibration
          2. 8.4.5.3.2 System Gain Calibration
        4. 8.4.5.4 Calibration Timing
    5. 8.5 Programming
      1. 8.5.1 Digital Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Ready (DRDY)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Reset
        7. 8.5.1.7 SPI Communication During Power-Down Mode
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  WAKEUP (0000 000x)
        2. 8.5.3.2  SLEEP (0000 001x)
        3. 8.5.3.3  SYNC (0000 010x)
        4. 8.5.3.4  RESET (0000 011x)
        5. 8.5.3.5  RDATA (0001 001x)
        6. 8.5.3.6  RDATAC (0001 010x)
        7. 8.5.3.7  SDATAC (0001 011x)
        8. 8.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 8.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 8.5.3.10 SYSOCAL (0110 0000)
        11. 8.5.3.11 SYSGCAL (0110 0001)
        12. 8.5.3.12 SELFOCAL (0110 0010)
        13. 8.5.3.13 NOP (1111 1111)
        14. 8.5.3.14 Restricted Command (1111 0001)
    6. 8.6 Register Maps
      1. 8.6.1 Register Map
      2. 8.6.2 Detailed Register Definitions
        1. 8.6.2.1  MUX0—Multiplexer Control Register 0 (address = 00h) [reset = 01h]
        2. 8.6.2.2  VBIAS—Bias Voltage Register (address = 01h) [reset = 00h]
        3. 8.6.2.3  MUX1—Multiplexer Control Register 1 (address = 02h) [reset = x0h]
        4. 8.6.2.4  SYS0—System Control Register 0 (address = 03h) [reset = 00h]
        5. 8.6.2.5  OFC—Offset Calibration Coefficient Register (address = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 8.6.2.6  FSC—Full-Scale Calibration Coefficient Register (address = 07h, 08h, 09h) [reset = 00h, 00h, 40h]
        7. 8.6.2.7  IDAC0—IDAC Control Register 0 (address = 0Ah) [reset = x0h]
        8. 8.6.2.8  IDAC1—IDAC Control Register 1 (address = 0Bh) [reset = FFh]
        9. 8.6.2.9  GPIOCFG—GPIO Configuration Register (address = 0Ch) [reset = 00h]
        10. 8.6.2.10 GPIODIR—GPIO Direction Register (address = 0Dh) [reset = 00h]
        11. 8.6.2.11 GPIODAT—GPIO Data Register (address = 0Eh) [reset = 00h]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Isolated (or Floating) Sensor Inputs
      6. 9.1.6 Unused Inputs and Outputs
      7. 9.1.7 Pseudo Code Example
      8. 9.1.8 Channel Multiplexing Example
      9. 9.1.9 Power-Down Mode Example
    2. 9.2 Typical Applications
      1. 9.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Topology
          2. 9.2.1.2.2 RTD Selection
          3. 9.2.1.2.3 Excitation Current
          4. 9.2.1.2.4 Reference Resistor (RREF)
          5. 9.2.1.2.5 PGA Setting
          6. 9.2.1.2.6 Common-Mode Input Range
          7. 9.2.1.2.7 Input and Reference Low-Pass Filters
          8. 9.2.1.2.8 Register Settings
        3. 9.2.1.3 Application Curves
      2. 9.2.2 K-Type Thermocouple Measurement (-200°C to +1250°C) With Cold-Junction Compensation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Biasing Resistors
          2. 9.2.2.2.2 Input Filtering
          3. 9.2.2.2.3 PGA Setting
          4. 9.2.2.2.4 Cold-Junction Measurement
          5. 9.2.2.2.5 Calculated Resolution
          6. 9.2.2.2.6 Register Settings
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档 
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The ADS1148-Q1 includes a low-noise, high-input impedance programmable gain amplifier (PGA), a delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an adjustable single-cycle settling digital filter, an internal oscillator, and an SPI-compatible serial interface.

The ADS1148-Q1 also includes a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a low-drift voltage reference, and two matched current sources for sensor excitation. The Functional Block Diagram section shows the various functions incorporated into ADS1148-Q1.

Functional Block Diagram

ADS1148-Q1 ai_fbd_sbas674.gif

Feature Description

ADC Input and Multiplexer

The ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. Figure 17 shows a block diagram of the analog input multiplexer.

The input multiplexer connects to eight analog inputs. Any analog input pin can be selected as the positive input or negative input through the MUX0 register. The multiplexer also allows the on-chip excitation current and bias voltage to be selected to a specific channel.

Through the input multiplexer, the ambient temperature (internal temperature sensor), AVDD, DVDD, and the external reference can all be selected for measurement. See the System Monitor section for more details.

The analog inputs can also be configured as general-purpose inputs and outputs (GPIOs). See the General-Purpose Digital I/O section for more details.

ADS1148-Q1 ai_input_mux_bas674.gif Figure 17. Analog Input Multiplexer Circuit

ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100 mV, and do not exceed AVDD by more than 100 mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs.

Equation 2. AVSS – 100 mV < V(AINX) < AVDD + 100 mV

Low-Noise PGA

The ADS1148-Q1 features a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 by the SYS0register. Figure 18 shows a simplified diagram of the PGA.

The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter, as shown in Figure 18. As with any PGA, ensure that the input voltage stays within the specified common-mode input range. The common-mode input (VCM) must be within the range shown in Equation 3.

Equation 3. ADS1148-Q1 q_ai_vcm_range_sbas453.gif
ADS1148-Q1 ai_pga_diagram_sbas426.gif Figure 18. Simplified Diagram of the PGA

Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4.

Equation 4. FSR = ±VREF / Gain

Table 3 shows the corresponding full-scale input ranges when using the internal 2.048-V reference.

Table 3. PGA Full-Scale Range

PGA GAIN SETTING FSR
1 ±2.048 V
2 ±1.024 V
4 ±0.512 V
8 ±0.256 V
16 ±0.128 V
32 ±0.064 V
64 ±0.032 V
128 ±0.016 V

PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 18 cannot swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUTP and OUTN are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5.

Equation 5. AVSS + 0.1 V ≤ V(OUTN), V(OUTP) ≤ AVDD – 0.1 V

Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AINP and AINN) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 19.

ADS1148-Q1 pga_cmvr_sbas426.gif Figure 19. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 6.

Equation 6. VCM = ½ (V(AINP) + V(AINN)) = ½ (V(OUTP) + V(OUTN))

The voltages at the PGA inputs (AINP and AINN) can be expressed as Equation 7 and Equation 8.

Equation 7. V(AINP) = VCM + ½ VIN
Equation 8. V(AINN) = VCM – ½ VIN

The output voltages (V(OUTP) and V(OUTN)) can then be calculated as Equation 9 and Equation 10.

Equation 9. V(OUTP) = VCM + ½ Gain × VIN
Equation 10. V(OUTN) = VCM – ½ Gain × VIN

The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12.

Equation 11. VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain × VIN (MAX)
Equation 12. VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain × VIN (MAX)

To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (VIN (MAX)) that occurs in the application must be used. VIN (MAX) can be less than the maximum possible full-scale value.

PGA Common-Mode Voltage Calculation Example

The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference of VREF = 2.5 V. The maximum possible differential input voltage VIN = (V(AINP) – V(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed VCM range of 1.35 V ≤ VCM ≤ 1.95 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to VIN (MAX) = ±0.1 V, for example, then this reduced input signal amplitude relaxes the VCM restriction to 0.9 V ≤ VCM ≤ 2.4 V.

In the case of a fully differential sensor signal, each input (AINP, AINN) can swing up to ±50 mV around the common-mode voltage (V(AINP) + V(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully differential signal. Figure 20 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (VCM) or increase in differential input voltage (VIN) drives V(OUTN) below 0.1 V and saturates amplifier A2.

ADS1148-Q1 pga_example_sbas426.gif Figure 20. Example Where VCM is at the Lowest Limit

In contrast, the signal of a resistance temperature detector (RTD) is of a pseudo-differential nature (if implemented as in the 3-Wire RTD Measurement System section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to VIN (MAX) = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time that the voltage on the positive input changes. That is, when the input signal swings between 0 V ≤ VIN ≤ VIN (MAX), the common-mode voltage swings between V(AINN) ≤ VCM ≤ V(AINN) + ½ VIN (MAX). Satisfying the common-mode voltage requirements for the maximum input voltage VIN (MAX) ensures the requirements are met throughout the entire signal range.

Figure 21 and Figure 22 show examples of both fully differential and pseudo-differential signals, respectively.

ADS1148-Q1 VCM_FullyDifferential_bas501.gif Figure 21. Fully Differential Input Signal
ADS1148-Q1 VCM_PseudoDifferential_bas501.gif Figure 22. Pseudo-Differential Input Signal

NOTE

With a unipolar power supply, the input range does not extend to the ground. Equation 11 and Equation 12 show the common-mode voltage requirements.

  • VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain × VIN (MAX)
  • VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain × VIN (MAX)

Analog Input Impedance

The device inputs are buffered through a high-input impedance PGA before reaching the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 4 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate.

Table 4. Typical Values for Analog Input Current Over Data Rate(1)

CONDITION ABSOLUTE INPUT CURRENT EFFECTIVE INPUT IMPEDANCE
DR = 5 SPS, 10 SPS, 20 SPS ± (0.5 nA + 0.1 nA/V) 5000 MΩ
DR = 40 SPS, 80 SPS, 160 SPS ± (2 nA + 0.5 nA/V) 1200 MΩ
DR = 320 SPS, 640 SPS, 1 kSPS ± (4 nA + 1 nA/V) 600 MΩ
DR = 2 kSPS ± (8 nA + 2 nA/V) 300 MΩ
Input current with VCM = 2.5 V, TA = 25°C, AVDD = 5 V, and AVSS = 0 V.

Clock Source

The device can use either the internal oscillator or an external clock. Connect the CLK pin to DGND before power-on or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator, with the device then operating on the external clock. After switching to the external clock, the device cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device.

Modulator

A third-order, delta-sigma modulator is used in the ADS1148-Q1. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. To save power, the modulator clock runs from 32 kHz up to 512 kHz for different data rates, as shown in Table 5.

Table 5. Modulator Clock Frequency for Different Data Rates

DATA RATE
(SPS)
MODULATOR RATE (fMOD)(1)
(kHz)
fCLK / fMOD
5, 10, 20 32 128
40, 80, 160 128 32
320, 640, 1000 256 16
2000 512 8
When using the internal oscillator or an external 4.096-MHz clock.

Digital Filter

The ADC uses linear-phase finite impulse response (FIR) digital filters that can be adjusted for different output data rates. The digital filter always settles in a single cycle.

Table 6 shows the exact data rates when an external clock equal to 4.096 MHz is used. Also shown is the signal –3-dB bandwidth, and the 50-Hz and 60-Hz attenuation. For good 50-Hz or 60-Hz rejection, use a data rate of 20 SPS or slower.

The frequency responses of the digital filter are illustrated in Figure 23 to Figure 33. Figure 26 illustrates a detailed view of the filter frequency response from 48 Hz to 62 Hz for a 20-SPS data rate. All filter plots are generated with a 4.096-MHz external clock.

Data rates and digital filter frequency responses scale proportionally with changes in the system clock frequency. The internal oscillator frequency has a variation, as specified in the Electrical Characteristics section, that also affects data rates and the digital filter frequency response.

Table 6. Digital Filter Specifications(1)

NOMINAL DATA RATE ACTUAL DATA RATE –3-dB BANDWIDTH ATTENUATION
fIN = 50 Hz ±0.3 Hz fIN = 60 Hz ±0.3 Hz fIN = 50 Hz ±1 Hz fIN = 60 Hz ±1 Hz
5 SPS 5.018 SPS 2.26 Hz –106 dB –74 dB –81 dB –69 dB
10 SPS 10.037 SPS 4.76 Hz –106 dB –74 dB –80 dB –69 dB
20 SPS 20.075 SPS 14.8 Hz –71 dB –74 dB –66 dB –68 dB
40 SPS 40.15 SPS 9.03 Hz
80 SPS 80.301 SPS 19.8 Hz
160 SPS 160.6 SPS 118 Hz
320 SPS 321.608 SPS 154 Hz
640 SPS 643.21 SPS 495 Hz
1000 SPS 1000 SPS 732 Hz
2000 SPS 2000 SPS 1465 Hz
Values shown are for fCLK = 4.096 MHz.
ADS1148-Q1 ai_filter_5sps_bas453.gif Figure 23. Filter Profile With Data Rate = 5 SPS
ADS1148-Q1 ai_filter_20sps_bas453.gif Figure 25. Filter Profile With Data Rate = 20 SPS
ADS1148-Q1 ai_filter_40sps_corrected_bas453.gif Figure 27. Filter Profile With Data Rate = 40 SPS
ADS1148-Q1 ai_filter_160sps_bas453.gif Figure 29. Filter Profile With Data Rate = 160 SPS
ADS1148-Q1 ai_filter_640sps_bas453.gif Figure 31. Filter Profile With Data Rate = 640 SPS
ADS1148-Q1 ai_filter_2ksps_bas453.gif Figure 33. Filter Profile With Data Rate = 2 kSPS
ADS1148-Q1 ai_filter_10sps_bas453.gif Figure 24. Filter Profile With Data Rate = 10 SPS
ADS1148-Q1 ai_filter_20_zoom_bas453.gif Figure 26. Detailed View of Filter Profile With
Data Rate = 20 SPS Between 48 Hz and 62 Hz
ADS1148-Q1 ai_filter_80sps_corrected_bas453.gif Figure 28. Filter Profile With Data Rate = 80 SPS
ADS1148-Q1 ai_filter_320sps_bas453.gif Figure 30. Filter Profile With Data Rate = 320 SPS
ADS1148-Q1 ai_filter_1ksps_bas453.gif Figure 32. Filter Profile With Data Rate = 1 kSPS

Voltage Reference Input

The voltage reference for the device is the differential voltage between REFP and REFN, given by Equation 13.

Equation 13. VREF = V(REFP) – V(REFN)

The ADS1148-Q1 has a multiplexer that selects the reference inputs, as shown in Figure 34. The reference inputs use buffers to increase the input impedance.

As with the analog inputs, REFP0 and REFN0 can also be configured as digital I/Os.

ADS1148-Q1 ai_ref_in_mux_bas674.gif Figure 34. Reference Input Multiplexer

The reference input circuit has ESD diodes to protect the inputs. To prevent the diodes from turning on, make sure the voltage on the reference input pin is not less than AVSS – 100 mV, and does not exceed AVDD + 100 mV, as shown in Equation 14.

Equation 14. AVSS – 100 mV < (V(REFP) or V(REFN)) < AVDD + 100 mV

Internal Voltage Reference

The ADS1148-Q1 has an internal voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048 V (nominal) with the capability of both sourcing and sinking up to 10 mA of current.

The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance must be in the range of 1 µF to 47 µF. Large values provide more filtering of the reference; however, the turn-on time increases with capacitance, as shown in Table 7. For stability reasons, VREFCOM must have a low-impedance path to an ac ground node. VREFCOM can be connected to AVSS (for a ±2.5-V analog power supply) as long as AVSS has a low-impedance path less than 10 Ω to an ac ground. In case this impedance is higher than 10 Ω, connect a capacitor of at least 0.1 µF between VREFCOM and the ac ground node.

NOTE

Take care when the device is turned off between conversions because time is required for the voltage reference to settle to the final voltage. Allow adequate time for the internal reference to fully settle before starting a new conversion.

Table 7. Internal Reference Settling Time

VREFOUT CAPACITOR SETTLING ERROR TIME TO REACH THE SETTLING ERROR
1 µF ±0.5% 70 µs
±0.1% 110 µs
4.7 µF ±0.5% 290 µs
±0.1% 375 µs
47 µF ±0.5% 2.2 ms
±0.1% 2.4 ms

The internal reference is controlled by the MUX1 register; by default, the internal reference is off after power up (see the Detailed Register Definitions section for more details). Therefore, the internal reference must first be turned on and then connected through the internal reference multiplexer. The internal reference is used to generate the current reference for the excitation current sources and hence must be turned on before the excitation currents become available.

Excitation Current Sources

The ADS1148-Q1 provides two matched excitation current sources (IDACs) for RTD applications. For three-wire RTD applications, the matched current sources can be used to cancel the errors caused by sensor lead resistance. The output current of the IDACs can be programmed to 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, 1000 µA, or 1500 µA.

The two matched current sources can be connected to the dedicated current output pins, IEXC1 and IEXC2; see the Detailed Register Definitions section for more information. Both current sources can be connected to the same pin. The internal reference must be turned on and the proper amount of capacitance applied to VREFOUT when using the excitation current sources.

Sensor Detection

To help detect a possible sensor malfunction, the device provides selectable current sources (0.5 µA, 2 µA, or 10 µA) to function as burn-out current sources. When enabled, one current source sources current to the selected positive analog input (AINP) and the other current source sinks current from the selected negative analog input (AINN).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor. The absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.

The ADC readings of a functional sensor can be corrupted when the burn-out current sources are enabled. The burn-out current sources are recommended to be disabled when performing a precision measurement, and are recommended to be enabled only to test for sensor fault conditions.

Bias Voltage Generation

A selectable bias voltage is provided for use with unbiased thermocouples. The bias voltage is (AVDD + AVSS) / 2 and can be applied to any analog input channel through the internal input multiplexer. Table 8 lists the bias voltage turn-on times for different sensor capacitances.

The internal bias voltage generator, when selected on multiple channels, causes the channels to be internally shorted. As a result, take care to limit the amount of current that can flow through the device. No more than 5 mA must be allowed to flow through this path, even if the device is in operation or powered down.

Table 8. Bias Voltage Settling Time

SENSOR CAPACITANCE SETTLING TIME
0.1 µF 220 µs
1 µF 2.2 ms
10 µF 22 ms
200 µF 450 ms

General-Purpose Digital I/O

The ADS1148-Q1 has eight pins that serve a dual purpose as either analog inputs or GPIOs.

Three registers control the function of the GPIO pins. Use the GPIO configuration register (IOCFG) to enable a pin as a GPIO pin. The GPIO direction register (IODIR) configures the GPIO pin as either an input or an output. Finally, the GPIO data register (IODAT) contains the GPIO data. If a GPIO pin is configured as an input, the respective IODAT[x] bit reads the status of the pin; if a GPIO pin is configured as an output, write the output status to the respective IODAT[x] bit. For more information about the use of GPIO pins, see the Detailed Register Definitions section.

Figure 35 shows a diagram of how these functions are combined onto a single pin. Note that when the pin is configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the ADS1148-Q1 is operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken during loading the GPIO pins when these pins are used as outputs because large currents can cause droop or noise on the analog supplies.

ADS1148-Q1 ai_ana_dig_int_pin_bas453.gif Figure 35. Analog and Data Interface Pin

System Monitor

The ADS1148-Q1 provides a system monitor function. This function can measure the analog power supply, digital power supply, external voltage reference, or ambient temperature. Note that the system monitor function provides a coarse result. When the system monitor is enabled, the analog inputs are disconnected.

Power-Supply Monitor

The system monitor can measure the analog or digital power supply. When measuring the power supply (VSP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15.

Equation 15. Conversion Result = (VSP / 4) / VREF

External Voltage Reference Monitor

The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (VREX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16.

Equation 16. Conversion Result = (VREX / 4) / VREF

NOTE

The internal reference voltage must be enabled when measuring an external voltage reference using the system monitor.

Ambient Temperature Monitor

On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at
TA = 25°C with a temperature coefficient of 405 µV/°C.

Device Functional Modes

Power Up

When DVDD is powered up, the internal power-on reset module generates a pulse that resets all digital circuitry. All digital circuits are held in a reset state for 216 system clocks to allow the analog circuits and the internal digital power supply to settle. SPI communication cannot occur until the internal reset is released.

Reset

When the RESET pin goes low, the device is immediately reset. All registers are restored to default values. The device stays in reset mode as long as the RESET pin stays low. When the RESET pin goes high, the ADC comes out of reset mode and is able to convert data. After the RESET pin goes high, the digital filter and the registers are held in a reset state for 0.6 ms when fCLK = 4.096 MHz. Therefore, valid SPI communication can only be resumed 0.6 ms after the RESET pin goes high; see Figure 4. When the RESET pin goes low, the clock selection is reset to the internal oscillator.

A reset can also be performed by the RESET command through the serial interface and is functionally the same as using the RESET pin. For information about using the RESET command, see the RESET section.

Power-Down Mode

Power consumption is reduced to a minimum by placing the device into power-down mode. There are two ways to put the device into power-down mode: using the SLEEP command and taking the START pin low.

During power-down mode, the internal reference status depends on the setting of the VREFCON bits in the MUX1 register; see the Register Maps section for details.

Conversion Control

The START pin provides precise control of conversions. Pulse the START pin high to begin a conversion, as described in Figure 36 and Table 9. The conversion completion is indicated by the DRDY pin going low and with the DOUT/DRDY pin when the DRDY MODE bit is 1 in the IDAC0 register. When the conversion completes, the device automatically powers down. During power down, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays powered down until the START pin is returned high to begin a new conversion. When the START pin returns high, the decimation filter is held in a reset state for 32 modulator clock cycles internally to allow the analog circuits to settle.

Holding the START pin high configures the device to continuously convert; see Figure 37.

ADS1148-Q1 ai_spi_start_single_conv_sbas674.gif Figure 36. Timing for a Single Conversion Using the START Pin

Table 9. START Pin Conversion Times for Figure 36 (1)

PARAMETER DATA RATE (SPS) VALUE UNIT
tCONV Time from START pulse to DRDY and DOUT/DRDY going low 5 200.295 ms
10 100.644 ms
20 50.825 ms
40 25.169 ms
80 12.716 ms
160 6.489 ms
320 3.247 ms
640 1.692 ms
1000 1.138 ms
2000 0.575 ms
For fCLK = 4.096 MHz.
ADS1148-Q1 ai_tim_start_high_bas674.gif

NOTE:

SCLK is held low in this example.
Figure 37. Timing for Conversion with the START Pin High

With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform synchronized measurements for multichannel applications by pulsing the START pin. With multiple devices, if each device receives the START pin pulse at the same time, all devices start a conversion when the START pin rises. If all devices are operating with the same data rate, all devices complete the conversion at the same time.

Conversions can also be initiated through SPI commands. Similar to using the START pin, the device can be put into a power-down mode using the SLEEP command. Functionally, this mode is similar to taking the START pin low. To initiate a conversion, the WAKEUP command powers up the ADC and starts a conversion, similar to returning the START pin high. Note that the START pin must be held high to use commands to control conversions. Do not combine using the START pin and using commands to control conversions.

Furthermore, sending a SYNC command immediately starts a new ADC conversion. For the SYNC command, the digital filter is reset, starting a new conversion without completing the previous conversion. This process is useful in synchronizing conversions from multiple devices or for maintaining periodic timing from multiple channels.

Similarly, writing to any of the first four registers (MUX0, VBIAS, MUX1, or SYS0; addresses 00h to 04h) automatically resets the digital filter. A change in any of these registers makes the appropriate setup change in the device, but also restarts the conversion similar to a SYNC command.

Settling Time for Channel Multiplexing

The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to the final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 10 for specific values.

Channel Cycling and Overload Recovery

When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overload condition cannot occur during the data transmission. When configuration register data are transferred to the device, new settings become active at the end of each byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before the completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, the communication may need to be split into two separate communications, thus allowing the SYS0 register to before the change of the MUX0 register.

In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Changing data rates during an overload state can cause the chopper to become unstable because the device implements a chopper-stabilized PGA. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate.

Single-Cycle Settling

The ADS1148-Q1 is capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between beginning to write a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 oscillator clocks before initiating another write command.

Digital Filter Reset Operation

Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or when the START pin is taken high.

The filter is reset four system clocks (tCLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write.

If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.

Table 10 lists the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.

Table 10. Data Conversion Time

NOMINAL DATA RATE (SPS) EXACT DATA RATE
(SPS)
FIRST DATA CONVERSION TIME AFTER FILTER RESET SECOND AND SUBSEQUENT CONVERSION TIME AFTER FILTER RESET
SYNC COMMAND, MUX0 REGISTER WRITE HARDWARE RESET, RESET COMMAND, START PIN HIGH, WAKEUP COMMAND, VBIAS, MUX1, OR SYS0 REGISTER WRITE
VALUE (ms)(1) NO. OF SYSTEM CLOCK CYCLES VALUE (ms)(1) NO. OF SYSTEM CLOCK CYCLES VALUE (ms)(1) NO. OF SYSTEM CLOCK CYCLES
5 5.019 199.258 816160 200.26 820265 199.250 816128
10 10.038 99.633 408096 100.635 412201 99.625 408064
20 20.075 49.820 204064 50.822 208169 49.812 204032
40 40.151 24.920 102072 25.172 103106 24.906 102016
80 80.301 12.467 51064 12.719 52098 12.453 51008
160 160.602 6.241 25560 6.492 26594 6.226 25504
320 321.608 3.124 12796 3.250 13314 3.109 12736
640 643.216 1.569 6428 1.695 6946 1.554 6368
1000 1000.000 1.014 4156 1.141 4674 1.000 4096
2000 2000.000 0.514 2108 0.578 2370 0.500 2048
For fCLK = 4.096 MHz.

Calibration

The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 38, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC) to digitally scale the gain. A digital clipping circuit ensures that the output code does not exceed 16 bits. Equation 17 shows the scaling.

ADS1148-Q1 ai_cali_fbd_bas453.gif Figure 38. Calibration Block Diagram
Equation 17. ADS1148-Q1 q_final_data_bas453.gif

The values of the offset and full-scale registers are set either by writing to them directly, or are set automatically by calibration commands.

The offset and gain calibration features are intended for the correction of minor system-level offset and gain errors. When entering manual values into the calibration registers, take care to avoid scaling down the gain register to values far below a scaling factor of 1.0. Under extreme situations, overranging the ADC is possible. Avoid encountering situations where analog inputs are connected to voltages greater than VREF / Gain.

Take care when increasing digital gain with the FSC register. When implementing custom digital gains less than 20% higher than nominal and offsets less than 40% of full scale, no special care is required. When operating at digital gains greater than 20% higher than nominal and offsets greater than 40% of full-scale, make sure that the offset and gain registers follow the conditions of Equation 18.

Equation 18. ADS1148-Q1 q_ai_digital_gain_sbas426.gif

Offset Calibration Register: OFC[2:0]

The offset calibration is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The upper 16 bits, OFC[2:1], are the most important bits of the offset calibration register for calibration and can correct offsets ranging from –FS to +FS, as shown in Table 11. The lower eight bits, OFC[0], provide sub-LSB correction and are used by the calibration commands. If a calibration command is issued and the offset register is then read for storage and re-use later, all 24 bits of the OFC are recommended to be used. When the calibration commands are not used and the offset is corrected by writing a user-calculated value to the OFC register, only OFC[2:1] are recommended to be used and OFC[0] is recommended to be left as all zeros. A register value of 000000h provides no offset correction.

Note that although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 11), avoid overloading the analog inputs.

Table 11. Final Output Code vs
Offset Calibration Register Setting

OFFSET REGISTER FINAL OUTPUT CODE WITH VIN = 0(1)
7FFFFFh 8000h
000100h FFFFh
000000h 0000h
FFFF00h 0001h
800000h 7FFFh
Excludes effects of noise and inherent offset errors.

Full-Scale Calibration Register: FSC[2:0]

The full-scale or gain calibration is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24 bits, straight binary, and normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the full-scale register. Note that although the full-scale calibration register can correct gain errors greater than 1 (with gain scaling less than 1), make sure to avoid overloading the analog inputs.

Table 12. Gain Correction Factor vs
Full-Scale Calibration Register Setting

FULL-SCALE REGISTER GAIN SCALING
800000h 2
400000h 1
200000h 0.5
000000h 0

Calibration Commands

The device provides commands for three types of calibration: system gain calibration, system offset calibration, and self offset calibration. Where absolute accuracy is required, a calibration is recommended to be performed after power up, a change in temperature, a change of gain, and in some cases a change in channel. At the completion of calibration the DRDY signal goes low, indicating that the calibration is complete. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the device powers down after completing calibration.

After a calibration starts, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this scenario occurs, either resend the calibration command that was aborted or issue a device reset.

System Offset and Self Offset Calibration

System offset calibration corrects both internal and external offset errors. The system offset calibration is initiated by sending the SYSOCAL command when applying a zero differential input voltage (VIN = 0 V) to the selected analog inputs with the inputs set within the specified input common-mode range, ideally at mid-supply.

The self offset calibration is initiated by sending the SELFOCAL command. During self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero differential signal is applied internally, thus connecting the inputs to mid-supply. With both offset calibrations, the offset calibration register (OFC) is updated afterwards. When either offset calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately. An offset calibration must be performed before a gain calibration.

System Gain Calibration

System gain calibration corrects for gain error in the signal path. The system gain calibration is initiated by sending the SYSGCAL command when applying a full-scale input to the selected analog inputs. Afterwards, the full-scale calibration register (FSC) is updated. When a system gain calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately.

Calibration Timing

When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This process provides a more accurate calibration value. The time required for calibration is shown in Table 13 and can be calculated using Equation 19.

Equation 19. ADS1148-Q1 q_cali_t_sbas426.gif

Table 13. Calibration Time versus Data Rate

DATA RATE
(SPS)
CALIBRATION TIME (tCAL)
(ms)(1)
5 3201.01
10 1601.01
20 801.012
40 400.26
80 200.26
160 100.14
320 50.14
640 25.14
1000 16.14
2000 8.07
For fCLK = 4.096 MHz.

Programming

Digital Interface

The device provides an SPI-compatible serial communication interface plus a data ready signal (DRDY). Communication is full-duplex with the exception of a few limitations in regards to the RREG command and the RDATA command. These limitations are explained in detail in the Commands section. For the basic serial interface timing characteristics, see Figure 1 and Figure 2.

Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reads and writes to the serial interface are ignored and the serial interface is reset. The DRDY pin operation is independent of CS. DRDY still indicates when a new conversion completes and is forced high in response to SCLK, even if CS is high.

Taking CS high only deactivates the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but SCLK is recommended to be kept as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and are shifted out of DOUT on the SCLK rising edge.

Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the SCLK falling edge.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is sent to the device when reading out data, send the no operation command (NOP) command on DIN.

Data Ready (DRDY)

The DRDY pin goes low to indicate that a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for tDTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, do not issue commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, DRDY is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after DRDY falls low, a short high pulse for a duration of tPWH indicates that new data are ready.

Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the IDAC0 register. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high.

When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the SCLK rising edge, MSB first (as shown in Figure 39).

When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode is not operational when the device is in stop read data continuous mode when the SDATAC command is given.

The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.

ADS1148-Q1 ai_tim_data_ret_dis_bas453.gif
CS tied low.
Figure 39. Data Retrieval With the DRDY MODE Bit = 0 (Disabled)

When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low. If DOUT/DRDY is already low, then this pin goes high and then goes low (as shown in Figure 40). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After DOUT/DRDY goes low, the data can be clocked out by providing 16 SCLKs if the device is in read data continuous mode. To force DOUT/DRDY high (so that DOUT/DRDY can be polled for a 0 instead of waiting for a falling edge), a NOP command or any other command that does not load the data output register can be sent after reading out the data. Because SCLKs can only be sent in multiples of eight, NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first SCLK rising edge after reading the conversion result completely (as shown in Figure 41). The same condition also applies after an RREG command. After all register bits are read out, the first SCLK rising edge forces DOUT/DRDY high. Figure 42 shows an example where sending an extra NOP command after reading out a register with an RREG command forces the DOUT/DRDY pin high.

ADS1148-Q1 ai_tim_data_ret_drdy_sbas453.gif
CS tied low.
Figure 40. Data Retrieval With the DRDY MODE Bit = 1 (Enabled)
ADS1148-Q1 ai_tim_dout_drdy_high_sbas453.gif
DRDY MODE bit enabled, CS tied low.
Figure 41. DOUT/DRDY Forced High After Retrieving the Conversion Result
ADS1148-Q1 ai_tim_dout_drdy_high_rreg_sbas426.gif
DRDY MODE bit enabled, CS tied low.
Figure 42. DOUT/DRDY Forced High After Reading Register Data

SPI Reset

SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. This process also returns all registers to the default values and starts a new conversion.

In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands are not recognized by the device. The device implements a timeout function for all listed commands in the Commands section in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout resets the interface if idle for 64 conversion cycles.

SPI Communication During Power-Down Mode

When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode.

Data Format

The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 20.

Equation 20. 1 LSB = (2 × VREF / Gain) / 216 = +FS / 215

A positive full-scale (FS) input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 14 summarizes the ideal output codes for different input signals.

Table 14. Ideal Output Code vs Input Signal

INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ FS (215 – 1) / 215 7FFFh
FS / 215 0001h
0 0000h
–FS / 215 FFFFh
≤ –FS 8000h
Excludes effects of noise, linearity, offset, and gain errors.

Figure 43 shows the mapping of the analog input signal to the output codes.

ADS1148-Q1 ai_code_trans_sbas453.gif Figure 43. Code Transition Diagram

Commands

The device offers 13 commands to control device operation, as shown in Table 15. Some of the commands are stand-alone commands (WAKEUP, SLEEP, SYNC, RESET, SYSOCAL, SYSGCAL, and SELFOCAL). There are three additional commands used to control reading of data from the device (RDATA, RDATAC, and SDATAC). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction. A NOP command can be used to clock out data from the device without clocking in a command.

Operands:

  • n = number of registers to be read or written (number of bytes – 1)
  • r = register (0 to 15)
  • x = don't care

Table 15. SPI Commands

COMMAND(1) DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE
WAKEUP Exit power down mode 0000 000x (00h, 01h)
SLEEP Enter power down mode 0000 001x (02h, 03h)
SYNC Synchronize ADC conversions 0000 010x (04h, 05h) 0000 010x (04,05h)
RESET Reset to default values 0000 011x (06h, 07h)
NOP No operation 1111 1111 (FFh)
RDATA Read data once 0001 001x (12h, 13h)
RDATAC Read data continuous mode 0001 010x (14h, 15h)
SDATAC Stop read data continuous mode 0001 011x (16h, 17h)
RREG Read from register rrrr 0010 rrrr (2xh) 0000 nnnn
WREG Write to register rrrr 0100 rrrr (4xh) 0000 nnnn
SYSOCAL System offset calibration 0110 0000 (60h)
SYSGCAL System gain calibration 0110 0001 (61h)
SELFOCAL Self offset calibration 0110 0010 (62h)
Restricted Restricted command.
Never send to the device.
1111 0001 (F1h)
Only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued when the START pin is low or when the device is in power-down mode.

WAKEUP (0000 000x)

Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK.

SLEEP (0000 001x)

The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in the MUX1 section for each device for further details.

To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device; see Figure 44.

NOTE

If the START pin is held low, a WAKEUP command does not power up the device. When using the SLEEP command, CS must be held low for the duration of the power-down mode.

ADS1148-Q1 ai_spi_sleep_wakeup_sbas426.gif Figure 44. SLEEP and WAKEUP Commands Operation

SYNC (0000 010x)

The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all devices simultaneously.

ADS1148-Q1 ai_spi_sync_sbas426.gif Figure 45. SYNC Command Operation

RESET (0000 011x)

The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchronization because of a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can only be started 0.6 ms after the RESET command is issued, as shown in Figure 46.

ADS1148-Q1 ai_spi_reset_sbas426.gif Figure 46. SPI Communication after an SPI Reset

RDATA (0001 001x)

The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 16 SCLKs, as shown in Figure 47. This command also works in RDATAC mode.

ADS1148-Q1 ai_read_once_bas453.gif Figure 47. RDATA: Reading Data Once Command

When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 48.

ADS1148-Q1 ai_tim_rdata_bas453.gif Figure 48. Using RDATA in Full-Duplex Mode

RDATAC (0001 010x)

The RDATAC command enables the read data continuous mode. This mode is the default mode after power-up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 16 SCLKs. Reading back all the bits is not necessary, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low and the command takes effect on the next DRDY, as shown in Figure 49.

Be sure to complete data retrieval (conversion result or register read back) before DRDY returns low, otherwise the resulting data are corrupted. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.

ADS1148-Q1 ai_read_cont_bas453.gif Figure 49. RDATAC: Read Data Continuously Command

SDATAC (0001 011x)

The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion.

RREG (0010 rrrr, 0000 nnnn)

The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The 2-byte command structure for RREG is listed below.

  • First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
  • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.
  • Byte: data read from the registers are clocked out with NOPs.

The full-duplex nature of the serial interface cannot be used when reading out register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 50. Any command sent during the readout of the register data is ignored. Thus, NOPs are recommended to be sent through DIN when reading out register data.

ADS1148-Q1 ai_read_reg_bas426.gif Figure 50. RREG: Read from Register Command

WREG (0100 rrrr, 0000 nnnn)

The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is:

  • First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
  • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.
  • Byte: data to be written to the registers.

ADS1148-Q1 ai_spi_wreg_sbas426.gif Figure 51. WREG: Write to Register Command

SYSOCAL (0110 0000)

The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common-mode range. The inputs must be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands is shown in Figure 52.

ADS1148-Q1 ai_calibration_command_sbas426.gif Figure 52. Calibration Command

SYSGCAL (0110 0001)

The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input must be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.

SELFOCAL (0110 0010)

The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.

NOP (1111 1111)

This command is a no-operation command. NOP is used to clock out data without clocking in a command.

Restricted Command (1111 0001)

This command is a restricted command. This command must never be issued to the device.

Register Maps

Register Map

Table 16. Register Map

REGISTER ADDRESS (HEX) REGISTER NAME REGISTER DATA
7 6 5 4 3 2 1 0
00h MUX0 BCS[1:0] MUX_SP[2:0] MUX_SN[2:0]
01h VBIAS VBIAS[7:0]
02h MUX1 CLKSTAT VREFCON[1:0] REFSELT[1:0] MUXCAL[2:0]
03h SYS0 0 PGA[2:0] DR[3:0]
04h OFC0 OFC[7:0]
05h OFC1 OFC[15:8]
06h OFC2 OFC[23:16]
07h FSC0 FSC[7:0]
08h FSC1 FSC[15:8]
09h FSC2 FSC[23:16]
0Ah IDAC0 ID[3:0] DRDY MODE IMAG[2:0]
0Bh IDAC1 I1DIR[3:0] I2DIR[3:0]
0Ch GPIOCFG IOCFG[7:0]
0Dh GPIODIR IODIR[7:0]
0Eh GPIODAT IODAT[7:0]

Detailed Register Definitions

MUX0—Multiplexer Control Register 0 (address = 00h) [reset = 01h]

This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

Figure 53. Multiplexer Control Register 0
7 6 5 4 3 2 1 0
BCS[1:0] MUX_SP[2:0] MUX_SN[2:0]
R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset

Table 17. Multiplexer Control Register 0 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 BCS[1:0] R/W 0h Burn-out detect current source register.
These bits control the setting of the sensor burnout detect current source.
00: Burn-out current source off (default)
01: Burn-out current source on, 0.5 µA
10: Burn-out current source on, 2 µA
11: Burn-out current source on, 10 µA
5-3 MUX_SP[2:0] R/W 0h Multiplexer selection, adc positive input.
These bits are the positive input channel selection bits.
000: AIN0 (default)
001: AIN1
010: AIN2
011: AIN3
100: AIN4
101: AIN5
110: AIN6
111: AIN7
2-0 MUX_SN[2:0] R/W 1h Multiplexer selection, adc negative input.
These bits are the negative input channel selection bits.
000: AIN0
001: AIN1 (default)
010: AIN2
011: AIN3
100: AIN4
101: AIN5
110: AIN6
111: AIN7

VBIAS—Bias Voltage Register (address = 01h) [reset = 00h]

Figure 54. Bias Voltage Register
7 6 5 4 3 2 1 0
VBIAS[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset

Table 18. Bias Voltage Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 VBIAS[7] R/W 0h VBIAS[7] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN7.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN7
6 VBIAS[6] R/W 0h VBIAS[6] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN6.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN6
5 VBIAS[5] R/W 0h VBIAS[5] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN5.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN5
4 VBIAS[4] R/W 0h VBIAS[4] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN4.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN4
3 VBIAS[3] R/W 0h VBIAS[3] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN3
2 VBIAS[2] R/W 0h VBIAS[2] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN2
1 VBIAS[1] R/W 0h VBIAS[1] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN1
0 VBIAS[0] R/W 0h VBIAS[0] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0.
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN0

MUX1—Multiplexer Control Register 1 (address = 02h) [reset = x0h]

Figure 55. Multiplexer Control Register 1
7 6 5 4 3 2 1 0
CLKSTAT VREFCON[1:0] REFSELT[1:0] MUXCAL[2:0]
R-xh R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. Multiplexer Control Register 0 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 CLKSTAT R xh Clock status.
This bit is read-only and indicates whether the internal oscillator or external clock is being used.
0: Internal oscillator in use
1: External clock in use
6-5 VREFCON[1:0] R/W 0h Internal reference control.
These bits control the internal voltage reference. These bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. Note that the internal reference is required for operation of the IDAC functions.
00: Internal reference is always off (default)
01: Internal reference is always on
10, 11: Internal reference is on when a conversion is in progress and powers down when the device receives a SLEEP command or the START pin is taken low
4-3 REFSELT[1:0] R/W 0h Reference select control.
These bits select the reference input for the ADC.
00: REFP0 and REFN0 reference inputs selected (default)
01: REFP1 and REFN1 reference inputs selected
10: Internal reference selected
11: Internal reference selected and internally connected to REFP0 and REFN0 input pins
2-0 MUXCAL[2:0](1) R/W 0h System monitor control.
These bits are used to select a system monitor. The MUXCAL selection supercedes selections from the MUX0, MUX1, and VBIAS registers (includes MUX_SP, MUX_SN, VBIAS, and reference input selections).
000: Normal operation (default)
001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2.
010: Gain calibration. The analog inputs are connected to the voltage reference.
011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device.
100: REF1 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP1) – V(REFN1)) / 4.
101: REF0 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP0) – V(REFN0)) / 4.
110: Analog supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (AVDD – AVSS) / 4.
111: Digital supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (DVDD – DGND) / 4.
When using either reference monitor, the internal reference must be enabled.

Table 20 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 20. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by the SYS0 register Normal operation
001 Set by the SYS0 register Inputs shorted to mid-supply (AVDD + AVSS) / 2
010 Forced to 1 V(REFP) – V(REFN) (full-scale)
011 Forced to 1 Temperature measurement diode
100 Forced to 1 (V(REFP1) – V(REFN1)) / 4
101 Forced to 1 (V(REFP0) – V(REFN0)) / 4
110 Forced to 1 (AVDD – AVSS) / 4
111 Forced to 1 (DVDD – DGND) / 4

SYS0—System Control Register 0 (address = 03h) [reset = 00h]

Figure 56. System Control Register 0
7 6 5 4 3 2 1 0
0 PGA[2:0] DR[3:0]
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. System Control Register 0 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 RESERVED R 0h Reserved.
Always write 0
6-4 PGA[2:0] R/W 0h Gain setting for the PGA.
These bits determine the gain of the PGA.
000: PGA = 1 (default)
001: PGA = 2
010: PGA = 4
011: PGA = 8
100: PGA = 16
101: PGA = 32
110: PGA = 64
111: PGA = 128
3-0 DR[3:0] R/W 0h Data output rate setting.
These bits determine the data output rate of the ADC.
0000: DR = 5 SPS (default)
0001: DR = 10 SPS
0010: DR = 20 SPS
0011: DR = 40 SPS
0100: DR = 80 SPS
0101: DR = 160 SPS
0110: DR = 320 SPS
0111: DR = 640 SPS
1000: DR = 1000 SPS
1001 to 1111: DR = 2000 SPS

OFC—Offset Calibration Coefficient Register (address = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register. Note that address 04h = 7-0, 05h = 15-8, and 06h = 23-16.

Figure 57. Offset Calibration Coefficient Register
7 6 5 4 3 2 1 0
OFC[7:0]
R/W-00h
15 14 13 12 11 10 9 8
OFC[15:8]
R/W-00h
23 22 21 20 19 18 17 16
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset

Table 22. Offset Calibration Coefficient Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
23-0 OFC[23:0] R/W 000000h Offset calibration register.
Three registers compose the ADC 24-bit offset calibration word and are in twos complement format. The upper 16 bits (OFC[23:8]) can correct offsets ranging from –FS to +FS, and the lower eight bits (OFC[7:0]) provide sub-LSB correction. The ADC subtracts the register value from the conversion result before full-scale operation.

FSC—Full-Scale Calibration Coefficient Register (address = 07h, 08h, 09h) [reset = 00h, 00h, 40h]

These bits make up the full-scale calibration coefficient register. Note that address 07h = 7-0, 08h = 15-8, and 09h = 23-16.

Figure 58. Full-Scale Calibration Coefficient Register
7 6 5 4 3 2 4 0
FSC[7:0]
R/W-00h
15 14 13 12 11 10 9 8
FSC[15:8]
R/W-00h
23 22 21 20 19 18 17 16
FSC[23:16]
R/W-40h
LEGEND: R/W = Read/Write; -n = value after reset

Table 23. Full-Scale Calibration Coefficient Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
23-0 FSC[23:0] R/W 400000h Full-scale calibration register.
Three registers compose the ADC 24-bit, full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value of the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result.

IDAC0—IDAC Control Register 0 (address = 0Ah) [reset = x0h]

Figure 59. IDAC Control Register 0
7 6 5 4 3 2 1 0
ID[3:0] DRDY MODE IMAG[2:0]
R-xh R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. IDAC Control Register 0 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 ID[3:0] R xh Revision identification.
Read-only, factory-programmed bits used for revision identification.
Note: The revision ID may change without notification
3 DRDY MODE R/W 0h Data ready mode setting.
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low.
0: DOUT/DRDY pin functions only as data out (default)
1: DOUT/DRDY pin functions both as data out and data ready, active low(1)
2-0 IMAG[2:0] R/W 0h IDAC excitation current magnitude.
The device has two excitation current sources (IDACs) that can be used for sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the internal reference to be on.
000: off (default)
001: 50 µA
010: 100 µA
011: 250 µA
100: 500 µA
101: 750 µA
110: 1000 µA
111: 1500 µA
Cannot be used in SDATAC mode.

IDAC1—IDAC Control Register 1 (address = 0Bh) [reset = FFh]

Figure 60. IDAC Control Register 1
7 6 5 4 3 2 1 0
I1DIR[3:0] I2DIR[3:0]
R/W-Fh R/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset

The two IDACs can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.

Table 25. IDAC Control Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 I1DIR[3:0] R/W Fh IDAC excitation current output 1.
These bits select the output pin for the first excitation current source.
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
10x0: IEXC1
10x1: IEXC2
11xx: Disconnected (default)
3-0 I2DIR[3:0] R/W Fh IDAC excitation current output 2.
These bits select the output pin for the second excitation current source.
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
10x0: IEXC1
10x1: IEXC2
11xx: Disconnected (default)

GPIOCFG—GPIO Configuration Register (address = 0Ch) [reset = 00h]

Figure 61. GPIO Configuration Register
7 6 5 4 3 2 1 0
IOCFG[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset

Table 26. GPIO Configuration Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 IOCFG[7] R/W 0h GPIO[7] (AIN7) pin configuration.
0: GPIO[7] is not enabled (default)
1: GPIO[7] is applied to AIN7
6 IOCFG[6] R/W 0h GPIO[6] (AIN6) pin configuration.
0: GPIO[6] is not enabled (default)
1: GPIO[6] is applied to AIN6
5 IOCFG[5] R/W 0h GPIO[5] (AIN5) pin configuration.
0: GPIO[5] is not enabled (default)
1: GPIO[5] is applied to AIN5
4 IOCFG[4] R/W 0h GPIO[4] (AIN4) pin configuration.
0: GPIO[4] is not enabled (default)
1: GPIO[4] is applied to AIN4
3 IOCFG[3] R/W 0h GPIO[3] (AIN3) pin configuration.
0: GPIO[3] is not enabled (default)
1: GPIO[3] is applied to AIN3
2 IOCFG[2] R/W 0h GPIO[2] (AIN2) pin configuration.
0: GPIO[2] is not enabled (default)
1: GPIO[2] is applied to AIN2
1 IOCFG[1] R/W 0h GPIO[1] (REFN0) pin configuration.
0: GPIO[1] is not enabled (default)
1: GPIO[1] is applied to REFN0
0 IOCFG[0] R/W 0h GPIO[0] (REFP0) pin configuration.
0: GPIO[0] is not enabled (default)
1: GPIO[0] is applied to REFP0

GPIODIR—GPIO Direction Register (address = 0Dh) [reset = 00h]

Figure 62. GPIO Direction Register
7 6 5 4 3 2 1 0
IODIR[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset

Table 27. GPIO Direction Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 IODIR[7] R/W 0h GPIO[7] (AIN7) pin direction.
This bit configures GPIO[7] as a GPIO input or GPIO output.
0: GPIO[7] is an output (default)
1: GPIO[7] is an input
6 IODIR[6] R/W 0h GPIO[6] (AIN6) pin direction.
This bit configures GPIO[6] as a GPIO input or GPIO output.
0: GPIO[6] is an output (default)
1: GPIO[6] is an input
5 IODIR[5] R/W 0h GPIO[5] (AIN5) pin direction.
This bit configures GPIO[5] as a GPIO input or GPIO output.
0: GPIO[5] is an output (default)
1: GPIO[5] is an input
4 IODIR[4] R/W 0h GPIO[4] (AIN4) pin direction.
This bit configures GPIO[4] as a GPIO input or GPIO output.
0: GPIO[4] is an output (default)
1: GPIO[4] is an input
3 IODIR[3] R/W 0h GPIO[3] (AIN3) pin direction.
This bit configures GPIO[3] as a GPIO input or GPIO output.
0: GPIO[3] is an output (default)
1: GPIO[3] is an input
2 IODIR[2] R/W 0h GPIO[2] (AIN2) pin direction.
This bit configures GPIO[2] as a GPIO input or GPIO output.
0: GPIO[2] is an output (default)
1: GPIO[2] is an input
1 IODIR[1] R/W 0h GPIO[1] (REFN0) pin direction.
This bit configures GPIO[1] as a GPIO input or GPIO output.
0: GPIO[1] is an output (default)
1: GPIO[1] is an input
0 IODIR[0] R/W 0h GPIO[0] (REFP0) pin direction.
This bit configures GPIO[0] as a GPIO input or GPIO output.
0: GPIO[0] is an output (default)
1: GPIO[0] is an input

GPIODAT—GPIO Data Register (address = 0Eh) [reset = 00h]

Figure 63. GPIO Data Register
7 6 5 4 3 2 1 0
IODAT[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset

Table 28. GPIO Data Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 IODAT[7] R/W 0h GPIO[7] (AIN7) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[7] is low (default)
1: GPIO[7] is high
6 IODAT[6] R/W 0h GPIO[6] (AIN6) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[6] is low (default)
1: GPIO[6] is high
5 IODAT[5] R/W 0h GPIO[5] (AIN5) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[5] is low (default)
1: GPIO[5] is high
4 IODAT[4] R/W 0h GPIO[4] (AIN4) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[4] is low (default)
1: GPIO[4] is high
3 IODAT[3] R/W 0h GPIO[3] (AIN3) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[3] is low (default)
1: GPIO[3] is high
2 IODAT[2] R/W 0h GPIO[2] (AIN2) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[2] is low (default)
1: GPIO[2] is high
1 IODAT[1] R/W 0h GPIO[1] (REFN0) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[1] is low (default)
1: GPIO[1] is high
0 IODAT[0] R/W 0h GPIO[0] (REFP0) pin data.
When configured as an output, a read to this bit returns the register value.
When configured as an input, a write to this bit only sets the register value.
0: GPIO[0] is low (default)
1: GPIO[0] is high