ZHCSMZ6B December   2020  – July 2022 ADC3664

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Interface/Mode Configuration
          1. 8.3.5.3.1 Configuration Example
        4. 8.3.5.4 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.5.3 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining steps can come in any order.

Table 8-7 Configuration steps for changing interface or decimation
STEPFEATUREADDRESSDESCRIPTION
1Output Interface0x07Select the output interface bit mapping depending on resolution and output interface.
Output Resolution2-wire1-wire1/2-wire
14-bit0x2B0x6C0x8D
16-bit0x4B
18-bit0x2B
20-bit0x4B
20x13Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00.
30x19Configure the FCLK frequency based on bypass/decimation and number of lanes used.
Bypass/DecSLVDSFCLK SRC
(D7)		FCLK DIV
(D4)		TOG FCLK
(D0)
Bypass/ Real Decimation2-wire010
1-wire000
1/2-wire000
Complex Decimation2-wire100
1-wire100
1/2-wire001
40x1BSelect the output interface resolution using the bit mapper (D5-D3).
50x20
0x21
0x22		Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution2-wire1-wire1/2-wire
Real Decimation14-bituse default0xFE000use default
16-bit0xFF000
18-bit0xFF800
20-bit 0xFFC00
Complex Decimation14-bit0xFFFFF0xFFFFF
16-bit
18-bit
20-bit
6 0x39..0x60
0x61..0x88		 Change output bit mapping for chA and chB if desired. This works also with the default interface selection.
7Decimation Filter0x24Enable the decimation filter
80x25Configure the decimation filter
90x2A/B/C/D
0x31/2/3/4		Program the NCO frequency for complex decimation (can be skipped for real decimation)
100x27
0x2E		Configure the complex output data stream (set both bits to 0 for real decimation)
SLVDSOP-Order (D4)Q-Delay (D3)
2-wire10
1-wire01
1/2-wire11
110x26Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.