ZHCSDC0A May   2014  – January 2015 ADC34J22 , ADC34J23 , ADC34J24 , ADC34J25

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Summary of Special Mode Registers
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics: ADC34J24, ADC34J25
    7. 7.7  Electrical Characteristics: ADC34J22, ADC34J23
    8. 7.8  Electrical Characteristics: General
    9. 7.9  AC Performance: ADC34J25
    10. 7.10 AC Performance: ADC34J24
    11. 7.11 AC Performance: ADC34J23
    12. 7.12 AC Performance: ADC34J22
    13. 7.13 Digital Characteristics
    14. 7.14 Timing Characteristics
    15. 7.15 Typical Characteristics: ADC34J25
    16. 7.16 Typical Characteristics: ADC34J24
    17. 7.17 Typical Characteristics: ADC34J23
    18. 7.18 Typical Characteristics: ADC34J22
    19. 7.19 Typical Characteristics: Common Plots
    20. 7.20 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Map
      1. 9.6.1 Serial Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Application and Implementation

10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 200 and Figure 201 show the impedance (Zin = Rin || Cin) across the ADC input pins.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 D024_SBAS663.gifFigure 200. Differential Input Resistance, RIN
ADC34J22 ADC34J23 ADC34J24 ADC34J25 D025_SBAS663.gifFigure 201. Differential Input Capacitance, CIN

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Drv_Crct_Lw_Inpt_Freq_BAS663.gifFigure 202. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application using two back-to-back coupled transformers is illustrated in Figure 202. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curve

Figure 203 shows the performance obtained by using the circuit shown in Figure 202.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 C001_BAS669.png
fS = 160 MSPS SNR = 70.3 dBFS
fIN = 10 MHz SFDR = 84 dBc
Figure 203. Performance FFT at 10 MHz (Low Input Frequency)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Drv_Crct_Md_Inpt_Freq_BAS663.gifFigure 204. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 204.

10.2.2.3 Application Curve

Figure 205 shows the performance obtained by using the circuit shown in Figure 204.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 C005_BAS669.png
fS = 160 MSPS SNR = 67.9 dBFS
fIN = 170 MHz SFDR = 84.1 dBc
Figure 205. Performance FFT at 170 MHz (Mid Input Frequency)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Drv_Crct_Hg_Inpt_Freq_BAS663.gifFigure 206. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 206.

10.2.3.3 Application Curve

Figure 207 shows the performance obtained by using the circuit shown in Figure 206.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 C009_BAS669.png
fS = 160 MSPS SNR = 63.1 dBFS
fIN = 450 MHz SFDR = 73 dBc
Figure 207. Performance FFT at 450 MHz (High Input Frequency)