3 Description

The ADC34DSO75 is a 14-bit, 3GSPS, quad channel analog to digital converter (ADC) with built-in event detection engine and internal capture memory to enable an integerated digital storage oscilliscope (DSO) feature set. The buffered analog inputs have an internal termination impedance of 100Ω or 200Ω and enable each ADC to achieve a full power input bandwidth of 3GHz (-3dB).

Each ADC channel has a dedicated event detection engine to control data capture and storage to on the chip memory for offload via OSPI. There are a number of event detection modes including absolute high threshold, low threshold, high and low threshold derived from an aquired baseline, slope based triggering, and pin based triggering. Each ADC34DSO75 chip has a 256KiB memory which can be partitioned across the four channels of the ADC. Once an event is detected, the samples corresponding to the event can be written to the memory. Along with the event data, an event header (96 bytes per event) is stored in the memory and contains information about the event captured such as the event mode, voltage at event, and timestamp. The number of samples to be stored for the events is programmable for each channel and is based on pre and post event window sizes. The events are timestamp via a 64-bit counter in the event detection engine running at the full sample clock rate. The device has per channel pins for pin based triggering of events and also event detection status on the pins. The ADC34DSO75 has two SYSREF outputs to enable simple mutli-device synchronization schemes.

The device configuration is done using the CSPI which is just a standard SPI bus. The on-chip memory is read out via an Octal Serial Peripheral Interface (OSPI). Multiple ADC chips can be daisy chained to enable a single (OSPI) interface to the host.

Functional Block Diagram