ZHCSDU1A May   2014  – June 2015 ADC32J42 , ADC32J43 , ADC32J44 , ADC32J45

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: ADC32J44, ADC32J45
    7. 7.7  Electrical Characteristics: ADC32J42, ADC32J43
    8. 7.8  AC Performance: ADC32J45
    9. 7.9  AC Performance: ADC32J44
    10. 7.10 AC Performance: ADC32J43
    11. 7.11 AC Performance: ADC32J42
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements
    14. 7.14 Typical Characteristics: ADC32J45
    15. 7.15 Typical Characteristics: ADC32J44
    16. 7.16 Typical Characteristics: ADC32J43
    17. 7.17 Typical Characteristics: ADC32J42
    18. 7.18 Typical Characteristics: Common Plots
    19. 7.19 Typical Characteristics: Contour Plots
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Descriptions
        1. 9.6.2.1  Register 01h (address = 01h)
        2. 9.6.2.2  Register 03h (address = 03h)
        3. 9.6.2.3  Register 04h (address = 04h)
        4. 9.6.2.4  Register 06h (address = 06h)
        5. 9.6.2.5  Register 07h (address = 07h)
        6. 9.6.2.6  Register 08h (address = 08h)
        7. 9.6.2.7  Register 09h (address = 09h)
        8. 9.6.2.8  Register 0Ah (address = 0Ah)
        9. 9.6.2.9  Register 0Bh (address = 0Bh)
        10. 9.6.2.10 Register 0Ch (address = 0Ch)
        11. 9.6.2.11 Register 0Dh (address = 0Dh)
        12. 9.6.2.12 Register 0Eh (address = 0Eh)
        13. 9.6.2.13 Register 0Fh (address = 0Fh)
        14. 9.6.2.14 Register 13h (address = 13h)
        15. 9.6.2.15 Register 15h (address = 15h)
        16. 9.6.2.16 Register 27h (address = 27h)
        17. 9.6.2.17 Register 2Ah (address = 2Ah)
        18. 9.6.2.18 Register 2Bh (address = 2Bh)
        19. 9.6.2.19 Register 2Fh (address = 2Fh)
        20. 9.6.2.20 Register 30h (address = 30h)
        21. 9.6.2.21 Register 31h (address = 31h)
        22. 9.6.2.22 Register 34h (address = 34h)
        23. 9.6.2.23 Register 3Ah (address = 3Ah)
        24. 9.6.2.24 Register 3Bh (address = 3Bh)
        25. 9.6.2.25 Register 3Ch (address = 3Ch)
        26. 9.6.2.26 Register 422h (address = 422h)
        27. 9.6.2.27 Register 434h (address = 434h)
        28. 9.6.2.28 Register 522h (address = 522h)
        29. 9.6.2.29 Register 534h (address = 534h)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Detailed Description

9.1 Overview

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design ans the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The ADC32J4x devices support subclass 0, 1, and 2 with interface data rates up to 3.2 Gbps.

9.2 Functional Block Diagram

ADC32J42 ADC32J43 ADC32J44 ADC32J45 fbd_sbas663.gif

9.3 Feature Description

9.3.1 Analog Inputs

The ADC32J4x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving a 50-Ω termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC32J4x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_dif_sinewave_clk_bas550.gif
NOTE: RT = termination resistor, if necessary.
Figure 148. Differential Sine-Wave Clock Driving Circuit
ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_lvds_clk_drv_bas550.gifFigure 149. LVDS Clock Driving Circuit
ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_lvpecl_clk_drv_bas550.gifFigure 150. LVPECL Clock Driving Circuit
ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_intclk_buffer_las900.gif
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 151. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 152. However, the clock inputs must be driven differentially for best performance, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_drv_cir_1end_las900.gifFigure 152. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is
86 dB for a 14-bit ADC. Thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies.

Equation 1. ADC32J42 ADC32J43 ADC32J44 ADC32J45 Eq_SNR_CLKJttr_BAS663.gif

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:

Equation 2. ADC32J42 ADC32J43 ADC32J44 ADC32J45 Eq_SNR_Lmtn_BAS663.gif

The total clock jitter (TJitter) has two components: the internal aperture jitter (200 fs for the device), is set by the noise of the clock input buffer, and the external clock. TJitter can be calculated with Equation 3:

Equation 3. ADC32J42 ADC32J43 ADC32J44 ADC32J45 Eq_Ttl_Clk_Jttr_BAS663.gif

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input, although a faster clock slew rate improves ADC aperture jitter. The devices have a thermal noise of 73.5 dBFS and an internal aperture jitter of 200 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 153.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 D036_SBAS664.gifFigure 153. SNR vs Frequency and Jitter

9.3.2.2 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 160-MHz clock; the divide-by-2 option supports a maximum input clock of 320 MHz and the divide-by-4 option supports a maximum input clock frequency of 640 MHz.

9.3.3 Power-Down Control

The power-down functions of the ADC32J4x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality, as shown in Table 2.

Table 2. Power-Down Modes

FUNCTION POWER CONSUMPTION (mW) WAKE-UP TIME (µs)
Global power-down 5 85
Standby 118 35

9.3.4 Internal Dither Algorithm

The ADC32J4x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect of using dither algorithms.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 D103_SBAS663.gif
fS = 160 MSPS, SNR = 72 dBFS, fIN = 70 MHz, SFDR = 95 dBc
Figure 154. FFT with Dither On
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D104_SBAS663.gif
fS = 160 MSPS, SNR = 72.5 dBFS, fIN = 70 MHz,
SFDR = 85 dBc
Figure 155. FFT with Dither Off

9.3.5 JESD204B Interface

The ADC32J4x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial transmitter, as shown in Figure 156. The data of each ADC are serialized by 20X using an internal PLL and then transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 JESD204B_Intrfc_BAS663.gifFigure 156. JESD204B Interface

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data encoding and the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data from the transport layer can be scrambled.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 JESD204B_Blck_BAS663.gifFigure 157. JESD204B Block

9.3.5.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by asserting the SYNC~ signal. When a logic high is detected on the SYNC~ input pins, the ADC32J4x starts transmitting comma (K28.5) characters to establish code group synchronization. When synchronization is complete, the receiving device de-asserts the SYNC~ signal and the ADC32J4x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32J4x transmits four multiframes, each containing K frames (K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data.

9.3.5.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADC32J4x supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled via SPI register writes and are located in address 26h (bits 7-6).

9.3.5.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

  • L is the number of lanes per link,
  • M is the number of converters per device,
  • F is the number of octets per frame clock period, and
  • S is the number of samples per frame.
Table 3 lists the available JESD204B format and valid range for the ADC32J4x. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

Table 3. LMFS Values and Interface Rate

L M F S MINIMUM ADC SAMPLING RATE (MSPS) MAXIMUM fSERDES (Mbps) MAXIMUM ADC SAMPLING RATE (Msps) MAXIMUM fSERDES (GSPS) MODE
2 2 2 1 15 300 160 3.2 20X (default)
1 2 4 1 10 400 80 3.2 40X

The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration can be changed from 20X (default) to 40X by setting the registers listed in Table 4.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 JESD_Frm_Assmbl_BAS663.gifFigure 158. JESD Frame Assembly

Table 4. Configuring 40X Mode

ADDRESS DATA
2Bh 01h
30h 11h

9.3.5.4 Digital Outputs

The ADC32J4x JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential 100-Ω load impedance and the termination resistors must be placed as close to the receiver inputs as possible to avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b and 10b encoding, the output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode voltages between the transmitter and receivers. Connect the termination resistors to the termination voltage, as shown in Figure 159.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 Dgtl_Otpts_BAS663.gifFigure 159. CML Output Connections

Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (156.25 MSPS, 20X mode), respectively.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 eye_3125gbps_las900.gifFigure 160. Eye Diagram: 3.125 Gbps

9.4 Device Functional Modes

9.4.1 Digital Gain

The input full-scale amplitude can be selected between 1 VPP to 2 VPP (default is 2 VPP) by choosing the appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for SFDR performance. A larger input full-scale increases SNR performance (2 VPP is recommended for maximum SNR) and a reduced input swing typically results in better SFDR performance. Table 5 lists the available digital gain settings.

Table 5. Digital Gain versus Full-Scale Amplitude

DIGITAL GAIN (dB) MAX INPUT VOLTAGE (VPP)
0 2
0.5 1.89
1 1.78
1.5 1.68
2 1.59
2.5 1.50
3 1.42
3.5 1.34
4 1.26
4.5 1.19
5 1.12
5.5 1.06
6 1.00

9.4.2 Overrange Indication

The ADC32J4x provides two different overrange indications. The normal OVR (default) is triggered if the final 14-bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRA, OVRB pins. The fast OVR indication can be presented on the overrange pins instead by using the SPI register map.

9.5 Programming

The ADC32J4x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial interface registers can be cleared during operation either:

  1. Through a hardware reset, or
  2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

  1. Drive the SEN pin low,
  2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
  3. Set bit A14 in the address field to 1,
  4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and
  5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 161 and Table 6 show the timing requirements for the serial register write operation.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 Srl_Rgstr_wrt_Tmg_BAS663.gifFigure 161. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing(1)

MIN TYP MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDIO setup time 25 ns
tDH SDIO hold time 25 ns
(1) Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted.

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. To read the contents of serial registers, follow this procedure:

  1. Drive the SEN pin low.
  2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
  3. Set bit A14 in the address field to 1.
  4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
  5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
  6. The external controller can latch the contents at the SCLK rising edge.
  7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 163.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 Srl_Rgstr_Rd_Tmg_BAS663.gifFigure 162. Serial Register Read Timing Diagram
ADC32J42 ADC32J43 ADC32J44 ADC32J45 ai_tim_sdout_las900.gifFigure 163. SDOUT Timing Diagram

9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 164 and Table 7.

ADC32J42 ADC32J43 ADC32J44 ADC32J45 Rgstr_Intlztn_BAS663.gifFigure 164. Initialization of Serial Registers after Power-Up

Table 7. Power-Up Timing

MIN TYP MAX UNIT
t1 Power-on delay from power-up to an active high RESET pulse 1 ms
t2 Reset pulse duration: active high RESET pulse duration 10 1000 ns
t3 Register write delay from RESET disable to SEN active 100 ns

If required, the serial interface registers can be cleared during operation either:

  1. Through hardware reset, or
  2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.3 Start-Up Sequence

After power-up, the sequence described in Table 8 can be used to set up the ADC32J4x for basic operation.

Table 8. Start-Up Settings

STEP DESCRIPTION REGISTER ADDRESS AND DATA
1 Provide all supply voltages. There is no required power-supply sequence for AVDD and DVDD.
2 Pulse a hardware reset (low to high to low) on pin 24
3 Optionally, configure LMFS of the JESD204B interface to LMFS = 1241 (default is LMFS = 2221) Address 2Bh, data 01h
Address 30h, data 11h
4 Pulse SYNC~ from high to low to transmit data from K28.5 SYNC~ mode

9.6 Register Maps

Table 9. Register Map Summary

REGISTER ADDRESS REGISTER DATA
A[13:0] (Hex) 7 6 5 4 3 2 1 0
01 0 0 DIS DITHER CHA DIS DITHER CHB 0 0
03 0 0 0 0 0 0 CHA GAINEN 0
04 0 0 0 0 0 0 CHB GAINEN 0
06 0 0 0 0 0 0 TEST PATTERN EN RESET
07 0 0 0 SPECIAL MODE1 CHA EN FOVR 0
08 0 0 0 SPECIAL MODE1 CHB 0 0
09 0 0 0 0 0 0 ALIGN TEST PATTERN DATA FORMAT
0A 0 0 0 0 CHA TEST PATTERN
0B CHB TEST PATTERN 0 0 0 0
0C 0 0 0 0 CHA DIGITAL GAIN
0D CHB DIGITAL GAIN 0 0 0 0
0E CUSTOM PATTERN[13:6]
0F CUSTOM PATTERN[5:0] 0 0 0
13 LOW SPEED MODE 0 0 0 0 0 0 0
15 0 CHA PDN CHB PDN 0 STANDBY GLOBAL PDN 0 CONFIG PDN PIN
27 CLK DIV 0 0 0 0 0 0
2A SERDES TEST PATTERN IDLE SYNC TRP LAYER
TESTMODE EN
FLIP ADC
DATA
LANE
ALIGN
FRAME ALIGN TXMIT LINKDATA
DIS
2B 0 0 0 0 0 0 CTRL K CTRL F
2F SCRAMBLE EN 0 0 0 0 0 0 0
30 OCTETS PER FRAME
31 0 0 0 FRAMES PER MULTIFRAME
34 SUBCLASSV 0 0 0 0 0
3A SYNC REG SYNC REQ EN 0 0 OUTPUT CURRENT SEL
3B LINK LAYER TESTMODE SEL[2:0] LINK LAYER RPAT 0 PULSE DET MODES
3C FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
422 0 0 0 0 0 0 SPECIAL
MODE2 CHA
0
434 0 0 DIS DITH CHA 0 DIS DITH CHA 0 0 0
522 0 0 0 0 0 0 SPECIAL
MODE2 CHB
0
534 0 0 DIS DITH CHB 0 DIS DITH CHB 0 0 0

9.6.1 Summary of Special Mode Registers

Table 10 lists the location, value, and functions of special mode registers in the device.

Table 10. Special Modes Summary

MODE LOCATION VALUE AND FUNCTION
Dither mode DIS DITH CHA 01h (bits 5-4), 434h (bits 5, 3) Creates a noise floor cleaner and improves SFDR;
see the Internal Dither Algorithm section.
0000 = Dither disabled
1111 = Dither enabled
DIS DITH CHB 01h (bits 3-2), 534h (bits 5, 3)
Special mode 1 SPECIAL MODE 1 CHA 07h (bits 4-2) Use for improved HD3.
000 = Default after reset
010 = Use for frequency < 120 MHz
111 = Use for frequency > 120 MHz
SPECIAL MODE 1 CHB 08h (bits 4-2)
Special mode 2 SPECIAL MODE 2 CHA 422h (bits 1-0) Helps improve HD2.
00 = Default after reset
11 = Improves HD2
SPECIAL MODE 2 CHB 522h (bits 1-0)

9.6.2 Serial Register Descriptions

9.6.2.1 Register 01h (address = 01h)

Figure 165. Register 01h
7 6 5 4 3 2 1 0
0 0 DIS DITHER CHA DIS DITHER CHB 0 0
W-0h W-0h R/W-0h R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 11. Register 01h Field Descriptions

Bit Field Type Reset Description
7-6 0 W 0h Must write 0.
5-4 DIS DITHER CHA R/W 0h These bits enable or disable the on-chip dither. Control these bits with bits 5 and 3 of register 434h.
00 = Dither enabled
11 = Dither disabled. Improves SNR by 0.4 dB for input frequencies up to 170 MHz.
3-2 DIS DITHER CHB R/W 0h These bits enable or disable the on-chip dither. Control these bits with bits 5 and 3 of register 534h.
00 = Dither enabled
11 = Dither disabled. Improves SNR by 0.4 dB for input frequencies up to 170 MHz.
1-0 0 W 0h Must write 0.

9.6.2.2 Register 03h (address = 03h)

Figure 166. Register 03h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 CHA GAINEN 0
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 12. Register 03h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 CHA GAINEN R/W 0h Digital gain enable bit for channel A.
0 = Digital gain disabled
1 = Digital gain enabled
0 0 W 0h Must write 0.

9.6.2.3 Register 04h (address = 04h)

Figure 167. Register 04h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 CHB GAINEN 0
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 13. Register 04h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 CHB GAINEN R/W 0h Digital gain enable bit for channel B.
0 = Digital gain disabled
1 = Digital gain enabled
0 0 W 0h Must write 0.

9.6.2.4 Register 06h (address = 06h)

Figure 168. Register 06h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 TEST PATTERN EN RESET
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 14. Register 06h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 TEST PATTERN EN R/W 0h This bit enables the test pattern selection for the digital outputs.
0 = Normal operation
1 = Test pattern output enabled
0 RESET R/W 0h Software reset applied.
This bit resets all internal registers to the default values and self-clears to 0.

9.6.2.5 Register 07h (address = 07h)

Figure 169. Register 07h
7 6 5 4 3 2 1 0
0 0 0 SPECIAL MODE1 CHA EN FOVR 0
W-0h W-0h W-0h R/W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 15. Register 07h Field Descriptions

Bit Field Type Reset Description
7-5 0 W 0h Must write 0.
4-2 SPECIAL MODE1 CHA R/W 0h 010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
1 EN FOVR R/W 0h 0 = Normal OVR on OVRx pins
1 = Enable fast OVR on OVRx pins
0 0 W 0h Must write 0.

9.6.2.6 Register 08h (address = 08h)

Figure 170. Register 08h
7 6 5 4 3 2 1 0
0 0 0 SPECIAL MODE1 CHB 0 0
W-0h W-0h W-0h R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 16. Register 08h Field Descriptions

Bit Field Type Reset Description
7-5 0 W 0h Must write 0.
4-2 SPECIAL MODE1 CHB R/W 0h 010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
1-0 0 W 0h Must write 0.

9.6.2.7 Register 09h (address = 09h)

Figure 171. Register 09h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 ALIGN TEST
PATTERN
DATA FORMAT
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 17. Register 09h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 ALIGN TEST PATTERN R/W 0h This bit aligns test patterns across the outputs of the four channels.
0 = Test patterns of four channels are free-running
1 = Test patterns of all four channels are aligned
0 DATA FORMAT R/W 0h This bit sets the digital output data format.
0 = Twos complement
1 = Offset binary

9.6.2.8 Register 0Ah (address = 0Ah)

Figure 172. Register 0Ah
7 6 5 4 3 2 1 0
0 0 0 0 CHA TEST PATTERN
W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 18. Register 0Ah Field Descriptions

Bit Field Type Reset Description
7-4 0 W 0h Must write 0.
3-0 CHA TEST PATTERN R/W 0h These bits control the test pattern for channel A after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399.
Others = Do not use

9.6.2.9 Register 0Bh (address = 0Bh)

Figure 173. Register 0Bh
7 6 5 4 3 2 1 0
CHB TEST PATTERN 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 19. Register 0Bh Field Descriptions

Bit Field Type Reset Description
7-4 CHB TEST PATTERN R/W 0h These bits control the test pattern for channel B after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399.
Others = Do not use
3-0 0 W 0h Must write 0.

9.6.2.10 Register 0Ch (address = 0Ch)

Figure 174. Register 0Ch
7 6 5 4 3 2 1 0
0 0 0 0 CHA DIGITAL GAIN
W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 20. Register 0Ch Field Descriptions

Bit Field Type Reset Description
7-4 0 W 0h Must write 0.
3-0 CHA DIGITAL GAIN R/W 0h These bits set the digital gain for individual channels. Register settings are listed in Table 21.

Table 21. Channel Digital Gain

REGISTER VALUE DIGITAL GAIN (dB) MAXIMUM INPUT VOLTAGE (VPP)
0000 0 2.0
0001 0.5 1.89
0010 1 1.78
0011 1.5 1.68
0100 2 1.59
0101 2.5 1.50
0110 3 1.42
0111 3.5 1.34
1000 4 1.26
1001 4.5 1.19
1010 5 1.12
1011 5.5 1.06
1100 6 1.00

9.6.2.11 Register 0Dh (address = 0Dh)

Figure 175. Register 0Dh
7 6 5 4 3 2 1 0
CHB DIGITAL GAIN 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 22. Register 0Dh Field Descriptions

Bit Field Type Reset Description
7-4 CHB DIGITAL GAIN R/W 0h These bits set the digital gain for the individual channels. Register settings are listed in Table 21.
3-0 0 W 0h Must write 0.

9.6.2.12 Register 0Eh (address = 0Eh)

Figure 176. Register 0Eh
7 6 5 4 3 2 1 0
CUSTOM PATTERN[13:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 23. Register 0Eh Field Descriptions

Bit Field Type Reset Description
7-0 CUSTOM PATTERN[13:6] R/W 0h These bits set the custom pattern[13:6] for all channels.

9.6.2.13 Register 0Fh (address = 0Fh)

Figure 177. Register 0Fh
7 6 5 4 3 2 1 0
CUSTOM PATTERN[5:0] 0 0
R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 24. Register 0Fh Field Descriptions

Bit Field Type Reset Description
7-2 CUSTOM PATTERN[5:0] R/W 0h These bits set the custom pattern[5:0] for all channels.
1-0 0 W 0h Must write 0.

9.6.2.14 Register 13h (address = 13h)

Figure 178. Register 13h
7 6 5 4 3 2 1 0
LOW SPEED MODE 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 25. Register 13h Field Descriptions

Bit Field Type Reset Description
7 LOW SPEED MODE R/W 0h Use this bit for sampling frequencies < 25 MSPS.
0 = Normal operation
1 = Low-speed mode is enabled
6-0 0 W 0h Must write 0.

9.6.2.15 Register 15h (address = 15h)

Figure 179. Register 15h
7 6 5 4 3 2 1 0
0 CHA PDN CHB PDN 0 STANDBY GLOBAL
PDN
0 PDN PIN
DISABLE
W-0h R/W-0h R/W-0h W-0h R/W-0h R/W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 26. Register 15h Field Descriptions

Bit Field Type Reset Description
7 0 W 0h Must write 0.
6 CHA PDN R/W 0h Power-down channel A.
0 = Normal operation
1 = Power-down channel A if the PDN PIN DISABLE register bit is set
5 CHB PDN R/W 0h Power-down channel B.
0 = Normal operation
1 = Power-down channel B if the PDN PIN DISABLE register bit is set
4 0 W 0h Must write 0.
3 STANDBY R/W 0h ADCs of both channels enter standby.
0 = Normal operation
1 = Standby
2 GLOBAL PDN R/W 0h Global power-down.
0 = Normal operation
1 = Global power-down
1 0 W 0h Must write 0.
0 PDN PINDISABLE R/W 0h This bit disables the power-down control from the pin.
0 = Normal operation
1 = Power-down pin is disabled; use register settings for power-down operations

9.6.2.16 Register 27h (address = 27h)

Figure 180. Register 27h
7 6 5 4 3 2 1 0
CLK DIV 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 27. Register 27h Field Descriptions

Bit Field Type Reset Description
7-6 CLK DIV R/W 0h Internal clock divider for the input sample clock.
00 = Clock divider bypassed
01 = Divide-by-1
10 = Divide-by-2
11 = Divide-by-4
5-0 0 W 0h Must write 0.

9.6.2.17 Register 2Ah (address = 2Ah)

Figure 181. Register 2Ah
7 6 5 4 3 2 1 0
SERDES TEST PATTERN IDLE SYNC TRP LAYER TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TX LINK CONFIG DATA DIS
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after

Table 28. Register 2Ah Field Descriptions

Bit Field Type Reset Description
7-6 SERDES TEST PATTERN R/W 0h 00 = Normal operation
01 = Outputs clock pattern: output is 10101010
10 = Encoded pattern: output is 1111111100000000
11 = PRBS sequence: output is 215 – 1
5 IDLE SYNC R/W 0h This bit sets the output pattern when SYNC~ is high.
0 = Sync code is K28.5 (BCBCh)
1 = Sync code is BC50h
4 TRP LAYER TESTMODE EN R/W 0h This bit generates the long transport layer test pattern mode according to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3 FLIP ADC DATA R/W 0h 0 = Normal operation
1 = Output data order is reversed: MSB – LSB
2 LANE ALIGN R/W 0h This bit inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1 FRAME ALIGN R/W 0h This bit inserts a frame alignment character (K28.7) for the receiver to align to the lane boundary per section 5.3.3.4 of the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0 TX LINK CONFIG DATA DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence when SYNC~ is de-asserted.
0 = Normal operation
1 = ILA disabled

9.6.2.18 Register 2Bh (address = 2Bh)

Figure 182. Register 2Bh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 CTRL K CTRL F
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 29. Register 2Bh Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 CTRL K R/W 0h Enable bit for the number of frames per multiframe.
0 = Default is 9 (20X mode) frames per multiframe
1 = Frames per multiframe can be set in register 31h
0 CTRL F R/W 0h Enable bit for the number of octets per frame.
0 = 20X mode using one lane per ADC (default is F = 2)
1 = Octets per frame can be specified in register 30h

9.6.2.19 Register 2Fh (address = 2Fh)

Figure 183. Register 2Fh
7 6 5 4 3 2 1 0
SCRAMBLE EN 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 30. Register 2Fh Field Descriptions

Bit Field Type Reset Description
7 SCRAMBLE EN R/W 0h Scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0 0 W 0h Must write 0.

9.6.2.20 Register 30h (address = 30h)

Figure 184. Register 30h
7 6 5 4 3 2 1 0
OCTETS PER FRAME
R/W-0h
LEGEND: R/W = Read/Write; -n = value after

Table 31. Register 30h Field Descriptions

Bit Field Type Reset Description
7-0 OCTETS PER FRAME R/W 0h These bits set the number of octets per frame (F).
01 = 20X serialization: two octets per frame
11 = 40X serialization: four octets per frame

9.6.2.21 Register 31h (address = 31h)

Figure 185. Register 31h
7 6 5 4 3 2 1 0
0 0 0 FRAMES PER MULTI FRAME
W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 32. Register 31h Field Descriptions

Bit Field Type Reset Description
7-5 0 W 0h Must write 0.
4-0 FRAMES PER MULTI FRAME R/W 0h These bits set the number of frames per multiframe.
After reset, the default settings for frames per multiframe are:
20X mode: K = 8
For each mode, K must not be set to a lower value.

9.6.2.22 Register 34h (address = 34h)

Figure 186. Register 34h
7 6 5 4 3 2 1 0
SUBCLASSV 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 33. Register 34h Field Descriptions

Bit Field Type Reset Description
7-5 SUBCLASSV R/W 0h JESD204B subclass setting.
000 = Subclass 0 backward compatibility with JESD204A
001 = Subclass 1 deterministic latency using the SYSREF signal
010 = Subclass 2 deterministic latency using SYNC~ detection
4-0 0 W 0h Must write 0.

9.6.2.23 Register 3Ah (address = 3Ah)

Figure 187. Register 3Ah
7 6 5 4 3 2 1 0
SYNC REQ SYNC REQ EN 0 0 OUTPUT CURRENT SEL
R/W-0h R/W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 34. Register 3Ah Field Descriptions

Bit Field Type Reset Description
7 SYNC REQ R/W 0h This bit generates a synchronization request only when the SYNC REQ EN register bit is set.
0 = Normal operation
1 = Generates sync request
6 SYNC REQ EN R/W 0h 0 = Sync request is made with the SYNCP~, SYNCM~ pins
1 = Sync request is made with the SYNC REQ register bit
5-4 0 W 0h Must write 0.
3-0 OUTPUT CURRENT SEL R/W 0h

JESD output buffer current selection.

0000 = 16 mA
0001 = 15 mA
0010 = 14 mA
0011 = 13 mA
0100 = 20 mA
0101 = 19 mA
0110 = 18 mA
0111 = 17 mA
1000 = 8 mA
1001 = 7 mA
1010 = 6 mA
1011 = 5 mA
1100 = 12 mA
1101 = 11 mA
1110 = 10 mA
1111 = 9 mA

9.6.2.24 Register 3Bh (address = 3Bh)

Figure 188. Register 3Bh
7 6 5 4 3 2 1 0
LINK LAYER TESTMODE LINK LAYER RPAT 0 PULSE DET MODES
R/W-0h R/W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 35. Register 3Bh Field Descriptions

Bit Field Type Reset Description
7-5 LINK LAYER TESTMODE R/W 0h These bits generate a pattern according to section 5.3.3.8.2 of the JESD204B specification.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences)
100 = 12 octet RPAT jitter pattern
4 LINK LAYER RPAT R/W 0h This bit changes the running disparity in the modified RPAT pattern test mode (only when link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3 0 W 0h Must write 0.
2-0 PULSE DET MODES R/W 0h These bits select different detection modes for SYSREF (subclass 1) and SYNC~ (subclass2). Register settings are listed in Table 36.

Table 36. PULSE DET MODES Register Settings

D2 D1 D0 FUNCTIONALITY
0 Don’t care 0 Allow all pulses to reset input clock dividers
1 Don’t care 0 Do not allow reset of analog clock dividers
Don’t care 0 to 1 transition 1 Allow one pulse immediately after the 0 to 1 transition to reset the divider

9.6.2.25 Register 3Ch (address = 3Ch)

Figure 189. Register 3Ch
7 6 5 4 3 2 1 0
FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILAN SEQ
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after

Table 37. Register 3Ch Field Descriptions

Bit Field Type Reset Description
7 FORCE LMFC COUNT R/W 0h 0 = Normal operation
1 = Enables using a different starting value for the LMFC counter
6-2 LMFC COUNT INIT R/W 0h If SYSREF is transmitted to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
1-0 RELEASE ILAN SEQ R/W 0h These bits delay the lane alignment sequence generation by 0, 1, 2, or 3 multiframes after the code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3

9.6.2.26 Register 422h (address = 422h)

Figure 190. Register 422h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 SPECIAL MODE2 CHA 0
W-0h W-0h W-0h W-0h W-0h W-0h W-1h W-0h
LEGEND: W = Write only; -n = value after

Table 38. Register 422h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 SPECIAL MODE2 CHA W 1h Always write 1 for improved HD2 performance.
0 0 W 0h Must write 0.

9.6.2.27 Register 434h (address = 434h)

Figure 191. Register 434h
7 6 5 4 3 2 1 0
0 0 DIS DITH CHA 0 DIS DITH CHA 0 0 0
W-0h W-0h R/W-0h W-0h R/W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 39. Register 434h Field Descriptions

Bit Field Type Reset Description
7-6 0 W 0h Must write 0.
5 DIS DITH CHA R/W 0h Set this bit along with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz.
4 0 W 0h Must write 0.
3 DIS DITH CHA R/W 0h Set this bit along with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz.
2-0 0 W 0h Must write 0.

9.6.2.28 Register 522h (address = 522h)

Figure 192. Register 522h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 SPECIAL MODE2 CHB 0
W-0h W-0h W-0h W-0h W-0h W-0h W-1h W-0h
LEGEND: W = Write only; -n = value after

Table 40. Register 522h Field Descriptions

Bit Field Type Reset Description
7-2 0 W 0h Must write 0.
1 SPECIAL MODE2 CHB W 1h Always write 1 for better HD2 performance.
0 0 W 0h Must write 0.

9.6.2.29 Register 534h (address = 534h)

Figure 193. Register 534
7 6 5 4 3 2 1 0
0 0 DIS DITH CHB 0 DIS DITH CHB 0 0 0
W-0h W-0h R/W-0h W-0h R/W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 41. Register 534 Field Descriptions

Bit Field Type Reset Description
7-6 0 W 0h Must write 0.
5 DIS DITH CHB R/W 0h Set this bit along with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz.
4 0 W 0h Must write 0.
3 DIS DITH CHB R/W 0h Set this bit along with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz.
2-0 0 W 0h Must write 0.