SNOI146C September   2011  – December 2017 ADC141S628-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 ADC141S628-Q1 Converter Electrical Characteristics
    5. 6.5 ADC141S628-Q1 Timing Requirements
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Reference Input (VREF)
      2. 7.2.2 Analog Signal Inputs
      3. 7.2.3 Pseudo-Differential Operation
      4. 7.2.4 Serial Digital Interface
      5. 7.2.5 CS Input
      6. 7.2.6 SCLK Input
      7. 7.2.7 Data Output
    3. 7.3 Device Functional Modes
      1. 7.3.1 Power Consumption
        1. 7.3.1.1 Short Cycling
        2. 7.3.1.2 Burst Mode Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Circuits
        1. 8.1.1.1 Data Acquisition
  9. Power Supply Recommendations
    1. 9.1 Analog and Digital Power Supplies
    2. 9.2 Voltage Reference
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Specification Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DGS|10
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

For best performance, care must be taken with the physical layout of the printed circuit board, which is especially true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so any noise must settle out before the conversion begins.

PCB Layout

Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated can have significant impact upon system noise performance. To avoid performance degradation of the ADC141S628-Q1 because of supply noise, avoid using the same supply for the VA and VREF of the ADC141S628-Q1 that is used for digital circuitry on the board.

Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. Clock lines must be kept as short as possible and isolated from all other lines, including other digital lines. In addition, the clock line must also be treated as a transmission line and be properly terminated. Isolate the analog input from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (for example, a filter capacitor) connected between the converter input pins and ground or to the reference input pin and ground must be connected to a very clean point in the ground plane.

A single, uniform ground plane and the use of split power planes are recommended. Place the power planes within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so forth) must be placed over the analog power plane. Place all digital circuitry over the digital power plane. Furthermore, the GND pins on the ADC141S628-Q1 and all the components in the reference circuitry and input signal chain that are connected to ground must be connected to the ground plane at a quiet point. Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device.