SNAS518J July   2011  – July 2015 ADC12D1800RF

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Functions
  4. Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 4.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 4.7  Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics
    8. 4.8  Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics
    9. 4.9  Converter Electrical Characteristics: Sampling Clock Characteristics
    10. 4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics
    11. 4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 4.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 4.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 4.14 Converter Electrical Characteristics: Serial Port Interface
    15. 4.15 Converter Electrical Characteristics Calibration
    16. 4.16 Typical Characteristics
  5. Detailed Description
    1. 5.1 Overview
      1. 5.1.1 RF Performance
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC/DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read / Write Calibration Settings
        7. 5.3.3.7 Calibration and Power-Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES/Non-DES Mode
      2. 5.4.2 Demux/Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC / DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
      1. 5.6.1 Register Definitions
  6. Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 LVDS Outputs
        1. 6.1.3.1 Common-mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1800RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 RF Sampling Receiver
      2. 6.2.2 Design Requirements
      3. 6.2.3 Detailed Design Procedure
      4. 6.2.4 Application Curves
  7. Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
  8. Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Specification Definitions
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Detailed Description

5.1 Overview

The ADC12D1800RF is a versatile A/D converter with an innovative architecture which permits very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in the Section 6.1 section. This section covers an overview, a description of control modes (Extended Control Mode and Non-Extended Control Mode), and features.

The ADC12D1800RF uses a calibrated folding and interpolating architecture that achieves a high Effective Number of Bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high performance, low power converter.

The analog input signal (which is within the converter's input voltage range) is digitized to twelve bits at speeds of 150 MSPS to 3.6 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of all ones. Either of these conditions at the I- or Q-input will cause the Out-of-Range I-channel or Q-channel output (ORI or ORQ), respectively, to output a logic-high signal.

In ECM, an expanded feature set is available via the Serial Interface. The ADC12D1800RF builds upon previous architectures, introducing a new DES Mode Timing Adjust, AutoSync feature for multi-chip synchronization and increasing to 15-bit for gain and 12-bit plus sign for offset the independent programmable adjustment for each channel.

Each channel has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demux Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demux Mode is selected, the output data rate on each channel is at the same rate as the input sample clock and only one 12-bit bus per channel is active.

5.1.1 RF Performance

ADC12D1800RF 30164398.gif
CW Blocker: Fin = 2675 MHz;
Total Power = –13 dBFS
WCDMA Blocker: Fc = 2685 MHz; Bandwidth = 3.84 MHz;
Total Power = –13 dBFS
IMD3 Product Power = -75 dBFS
Figure 5-1 ADC12D1800RF Non-DES Mode IMD3
ADC12D1800RF 30164314.gifFigure 5-2 ADC12D1800RF DES Mode FFT

5.2 Functional Block Diagram

ADC12D1800RF 30164311.png

5.3 Feature Description

The ADC12D1800RF offers many features to make the device convenient to use in a wide variety of applications. Table 5-1 is a summary of the features available, as well as details for the control mode chosen. "N/A" means "Not Applicable."

Table 5-1 Features and Modes

Feature Non-ECM Control Pin
Active in ECM
ECM Default ECM State
Input Control and Adjust
AC/DC-coupled Mode Selection Selected via VCMO
(Pin C2)
Yes Not available N/A
Input Full-scale Range Adjust Selected via FSR
(Pin Y3)
No Selected via the Config Reg
(Addr: 3h and Bh)
Low FSR value
Input Offset Adjust Setting Not available N/A Selected via the Config Reg
(Addr: 2h and Ah)
Offset = 0 mV
DES/Non-DES Mode Selection Selected via DES
(Pin V5)
No Selected via the DES Bit
(Addr: 0h; Bit: 7)
Non-DES Mode
DES Mode Input Selection Not available N/A Selected via the DCK Bit
(Addr: Eh; Bit: 6)
N/A
DESCLKIQ Mode(2) Not available N/A Selected via the DES Timing Adjust Reg
(Addr: 7h)
N/A
DES Timing Adjust Not available N/A Selected via the DES Timing Adjust Reg (Addr: 7h) Mid skew offset
Sampling Clock Phase
Adjust(1)
Not available N/A Selected via the Config Reg
(Addr: Ch and Dh)
tAD adjust disabled
Output Control and Adjust
DDR Clock Phase Selection Selected via DDRPh
(Pin W4)
No Selected via the DPS Bit
(Addr: 0h; Bit: 14)
0° Mode
DDR / SDR DCLK Selection Not available N/A Selected via the SDR Bit
(Addr: 0h; Bit: 2)
DDR Mode
SDR Rising / Falling DCLK Selection(2) Not available N/A Selected via the DPS Bit
(Addr: 0h; Bit: 14)
N/A
LVDS Differential Voltage Amplitude Selection Higher amplitude only N/A Selected via the OVS Bit
(Addr: 0h; Bit: 13)
Higher amplitude
LVDS Common-Mode Voltage Amplitude Selection(2) Selected via VBG
(Pin B1)
Yes Not available N/A
Output Formatting Selection (2) Offset Binary only N/A Selected via the 2SC Bit
(Addr: 0h; Bit: 4)
Offset Binary
Test Pattern Mode at Output Selected via TPM
(Pin A4)
No Selected via the TPM Bit
(Addr: 0h; Bit: 12)
TPM disabled
Demux/Non-Demux Mode Selection Selected via NDM
(Pin A5)
Yes Not available N/A
AutoSync Not available N/A Selected via the Config Reg
(Addr: Eh)
Master Mode,
RCOut1/2 disabled
DCLK Reset Not available N/A Selected via the Config Reg
(Addr: Eh; Bit 0)
DCLK Reset disabled
Time Stamp Not available N/A Selected via the TSE Bit
(Addr: 0h; Bit: 3)
Time Stamp disabled
Calibration
On-command Calibration Selected via CAL
(Pin D6)
Yes Selected via the CAL Bit
(Addr: 0h; Bit: 15)
N/A
(CAL = 0)
Power-on Calibration Delay Selection(2) Selected via CalDly
(Pin V4)
Yes Not available N/A
Calibration Adjust(2) Not available N/A Selected via the Config Reg
(Addr: 4h)
tCAL
Read / Write Calibration Settings(2) Not available N/A Selected via the SSC Bit
(Addr: 4h; Bit: 7)
R/W calibration values disabled
Power-Down
Power down I-channel Selected via PDI
(Pin U3)
Yes Selected via the PDI Bit
(Addr: 0h; Bit: 11)
I-channel operational
Power down Q-channel Selected via PDQ
(Pin V3)
Yes Selected via the PDQ Bit
(Addr: 0h; Bit: 10)
Q-channel operational
(1) Sampling Clock Phase Adjust cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) at CLK frequencies above 1600 MHz.

5.3.1 Input Control and Adjust

There are several features and configurations for the input of the ADC12D1800RF so that it may be used in many different applications. This section covers AC/DC-coupled Mode, input full-scale range adjust, input offset adjust, DES/Non-DES Mode, DES Timing Adjust, and sampling clock phase adjust.

5.3.1.1 AC/DC-coupled Mode

The analog inputs may be AC or DC-coupled. See Section 5.5.1.1.10 for information on how to select the desired mode and Section 6.1.1.7 and Section 6.1.1.6 for applications information.

5.3.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC12D1800RF may be adjusted in ECM. In Non-ECM, the control pin must be set to logic-high; see Section 5.5.1.1.9. In ECM, the input full-scale range may be adjusted with 15-bits of precision. See VIN_FSR in Section 4.7 for electrical specification details. Note that the full-scale input range setting in Non-ECM (logic-high only) corresponds to the lowest full-scale input range settings in ECM. It is necessary to execute an on-command calibration following a change of the input full-scale range. See Section 5.6.1 for information about the registers.

5.3.1.3 Input Offset Adjust

The input offset adjust for the ADC12D1800RF may be adjusted with 12-bits of precision plus sign via ECM. See Section 5.6.1 for information about the registers.

5.3.1.4 DES Timing Adjust

The performance of the ADC12D1800RF in DES Mode depends on how well the two channels are interleaved, i.e. that the clock samples either channel with precisely a 50% duty-cycle, each channel has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1800RF includes an automatic clock phase background adjustment in DES Mode to automatically and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the residual fixed timing skew offset may be further manually adjusted, and further reduce timing spurs for specific applications. See the Table 5-17 (Addr: 7h). As the DES Timing Adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur will decrease to a local minimum and then increase again. The default, nominal setting of 64d may or may not coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving spur.

5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust

NOTE

Sampling Clock Phase Adjust cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) at CLK frequencies above 1600 MHz.

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase array antennas.

Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust. Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in his system before relying on it.

Using this feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.

5.3.2 Output Control and Adjust

There are several features and configurations for the output of the ADC12D1800RF so that it may be used in many different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage, output formatting, Demux/Non-demux Mode, Test Pattern Mode, and Time Stamp.

5.3.2.1 SDR / DDR Clock

The ADC12D1800RF output data can be delivered in Double Data Rate (DDR) or Single Data Rate (SDR). For DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 5-3. The DCLK-to-Data phase relationship may be either 0° or 90°. For 0° Mode, the Data transitions on each edge of the DCLK. Any offset from this timing is tOSK; see Section 4.13 for details. For 90° Mode, the DCLK transitions in the middle of each Data cell. Setup and hold times for this transition, tSU and tH, may also be found in Section 4.13. The DCLK-to-Data phase relationship may be selected via the DDRPh Pin in Non-ECM (see Section 5.5.1.1.3) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM. Note that for Non-Demux Mode, 90° DDR Mode is not available.

ADC12D1800RF 30164394.gifFigure 5-3 DDR DCLK-to-Data Phase Relationship

For SDR, the DCLK frequency is the same as the data rate and data is sent to the outputs on a single edge of DCLK; see Figure 5-4. The Data may transition on either rising or falling edge of DCLK. Any offset from this timing is tOSK; see Section 4.13 for details. The DCLK rising / falling edge may be selected via the SDR bit in the Configuration Register (Addr: 0h; Bit: 2) in ECM only. Note that SDR is available in Demux Mode, but not in Non-Demux Mode.

ADC12D1800RF 30164315.gifFigure 5-4 SDR DCLK-to-Data Phase Relationship

5.3.2.2 LVDS Output Differential Voltage

The ADC12D1800RF is available with a selectable higher or lower LVDS output differential voltage. This parameter is VOD and may be found in Section 4.11. The desired voltage may be selected via the OVS Bit (Addr: 0h, Bit 13). For many applications, in which the LVDS outputs are very close to an FPGA on the same board, for example, the lower setting is sufficient for good performance; this will also reduce the possibility for EMI from the LVDS outputs to other signals on the board. See Section 5.6.1 for more information.

5.3.2.3 LVDS Output Common-Mode Voltage

The ADC12D1800RF is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is VOS and may be found in Section 4.11. See Section 5.5.1.1.11 for information on how to select the desired voltage.

5.3.2.4 Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting is offset binary, but two's complement may be selected via the 2SC Bit (Addr: 0h, Bit 4); see Section 5.6.1 for more information.

5.3.2.5 Test Pattern Mode

The ADC12D1800RF can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is programmed into the Demux Mode, the test pattern’s order is described in Table 5-2. If the I- or Q-channel is powered down, the test pattern will not be output for that channel.

Table 5-2 Test Pattern by Output Port in
Demux Mode(1)

Time Qd Id Q I ORQ ORI Comments
T0 000h 004h 008h 010h 0b 0b Pattern Sequence
n
T1 FFFh FFBh FF7h FEFh 1b 1b
T2 000h 004h 008h 010h 0b 0b
T3 FFFh FFBh FF7h FEFh 1b 1b
T4 000h 004h 008h 010h 0b 0b
T5 000h 004h 008h 010h 0b 0b Pattern Sequence
n+1
T6 FFFh FFBh FF7h FEFh 1b 1b
T7 000h 004h 008h 010h 0b 0b
T8 FFFh FFBh FF7h FEFh 1b 1b
T9 000h 004h 008h 010h 0b 0b
T10 000h 004h 008h 010h 0b 0b Pattern Sequence
n+2
T11 FFFh FFBh FF7h FEFh 1b 1b
T12 000h 004h 008h 010h 0b 0b
T13 ... ... ... ... ... ...
(1) When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 5-3.

Table 5-3 Test Pattern by Output Port in
Non-Demux Mode

Time Q I ORQ ORI Comments
T0 000h 004h 0b 0b Pattern
Sequence
n
T1 000h 004h 0b 0b
T2 FFFh FFBh 1b 1b
T3 FFFh FFBh 1b 1b
T4 000h 004h 0b 0b
T5 FFFh FFBh 1b 1b
T6 000h 004h 0b 0b
T7 FFFh FFBh 1b 1b
T8 FFFh FFBh 1b 1b
T9 FFFh FFBh 1b 1b
T10 000h 004h 0b 0b Pattern
Sequence
n+1
T11 000h 004h 0b 0b
T12 FFFh FFBh 1b 1b
T13 FFFh FFBh 1b 1b
T14 ... ... ... ...

5.3.2.6 Time Stamp

The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal. When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.

5.3.3 Calibration Feature

The ADC12D1800RF calibration must be run to achieve specified performance. The calibration procedure is exactly the same regardless of how it was initiated or when it is run. Calibration trims the analog input differential termination resistors, the CLK input resistor, and sets internal bias currents which affect the linearity of the converter. This minimizes full-scale error, offset error, DNL and INL, which results in the maximum dynamic performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB.

5.3.3.1 Calibration Control Pins and Bits

Table 5-4 is a summary of the pins and bits used for calibration. See Section 3.1.1 for complete pin information and Figure 4-7 for the timing diagram.

Table 5-4 Calibration Pins

Pin (Bit) Name Function
D6
(Addr: 0h; Bit 15)
CAL
(Calibration)
Initiate calibration
V4 CalDly
(Calibration Delay)
Select power-on calibration delay
(Addr: 4h) Calibration Adjust Adjust calibration sequence
B5 CalRun
(Calibration Running)
Indicates while calibration is running
C1/D2 Rtrim±
(Input termination trim resistor)
External resistor used to calibrate analog and CLK inputs
C3/D3 Rext±
(External Reference resistor)
External resistor used to calibrate internal linearity

5.3.3.2 How to Execute a Calibration

Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, and then holding it high for at least another tCAL_H clock cycles, as defined in Section 4.15. The minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as tCAL. The CAL Pin is active in both ECM and Non-ECM. However, in ECM, the CAL Pin is logically OR'd with the CAL Bit, so both the pin and bit are required to be set low before executing another calibration via either pin or bit.

5.3.3.3 Power-on Calibration

For standard operation, power-on calibration begins after a time delay following the application of power, as determined by the setting of the CalDly Pin and measured by tCalDly (see Section 4.15). This delay allows the power supply to come up and stabilize before the power-on calibration takes place. The best setting (short or long) of the CalDly Pin depends upon the settling time of the power supply.

It is strongly recommended to set CalDly Pin (to either logic-high or logic-low) before powering the device on since this pin affects the power-on calibration timing. This may be accomplished by setting CalDly via an external 1kΩ resistor connected to GND or VA. If the CalDly Pin is toggled while the device is powered-on, it can execute a calibration even though the CAL Pin / Bit remains logic-low.

The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1800RF will function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired.

If it is necessary to toggle the CalDly Pin during the system power up sequence, then the CAL Pin / Bit must be set to logic-high before the toggling and afterwards for 109 Sampling Clock cycles. This will prevent the power-on calibration, so an on-command calibration must be executed or the performance will be impaired.

5.3.3.4 On-command Calibration

In addition to the power-on calibration, it is recommended to execute an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance. Some examples include: changing the FSR via ECM, power-cycling either channel, and switching into or out of DES Mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, it is recommended to avoid unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the Serial Interface or use the DCLK Reset feature while calibrating the ADC. Doing so will impair the performance of the device until it is re-calibrated correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

5.3.3.5 Calibration Adjust

The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration time than the default is required; see tCAL in Section 4.15. However, the performance of the device, when using this feature is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, Bit 14). The default setting of CSS = 1b executes both RIN and RIN_CLK Calibration (using Rtrim) and internal linearity Calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity Calibration. The first time that Calibration is executed, it must be with CSS = 1b to trim RIN and RIN_CLK. However, once the device is at its operating temperature and RIN has been trimmed at least one time, it will not drift significantly. To save time in subsequent calibrations, trimming RIN and RIN_CLK may be skipped, i.e. by setting CSS = 0b.

5.3.3.6 Read / Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration, tCAL, or to allow for re-use of a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, RIN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally determined by the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2... R239 where R0 is a dummy value. The contents of R<239:1> should be stored.

4. Set SSC (Addr: 4h, Bit 7) to 0.

5. Continue with normal operation.

To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which Calibration Values were previously read.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written R1, R2, ... , R239.

4. Make two additional dummy writes of 0000h.

5. Set SSC (Addr: 4h, Bit 7) to 0.

6. Continue with normal operation.

5.3.3.7 Calibration and Power-Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1800RF will immediately power down. The calibration cycle will continue when either or both channels are powered back up, but the calibration will be compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration should be executed upon powering the ADC12D1800RF back up. In general, the ADC12D1800RF should be recalibrated when either or both channels are powered back up, or after one channel is powered down. For best results, this should be done after the device has stabilized to its operating temperature.

5.3.3.8 Calibration and the Digital Outputs

During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-low, it takes an additional 60 Sampling Clock cycles before the output of the ADC12D1800RF is valid converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes.

5.3.4 Power Down

On the ADC12D1800RF, the I- and Q-channels may be powered down individually. This may be accomplished via the control pins, PDI and PDQ, or via ECM. In ECM, the PDI and PDQ pins are logically OR'd with the Control Register setting. See Section 5.5.1.1.6 andSection 5.5.1.1.7 for more information.

5.4 Device Functional Modes

The ADC12D1800RF has two functional modes for sampling the input signal, DES mode and Non-DES mode and two mode to output sample data, Demux mode and Non-Demux Mode.

5.4.1 DES/Non-DES Mode

The ADC12D1800RF can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode allows for a single analog input to be sampled by both I- and Q-channels. One channel samples the input on the rising edge of the sampling clock and the other samples the same input signal on the falling edge of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the sampling clock frequency, e.g. 3.6 GSPS with a 1.8 GHz sampling clock. Since DES Mode uses both I- and Q-channels to process the input signal, both channels must be powered up for the DES Mode to function properly.

In Non-ECM, only the I-input may be used for the DES Mode input. See Section 5.5.1.1.1 for information on how to select the DES Mode. In ECM, either the I- or Q-input may be selected by first using the DES bit (Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr: 0h, Bit: 6) is used to select the Q-input, but the I-input is used by default. Also, both I- and Q-inputs may be driven externally, i.e. DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See Section 6.1.1 for more information about how to drive the ADC in DES Mode.

In DESCLKIQ Mode, the I- and Q-channels sample their inputs 180° out-of-phase with respect to one another, similar to the other DES Modes. DESCLKIQ Mode is similar to the DESIQ Mode, except that the I- and Q-channels remain electrically separate internal to the ADC12D1800RF. For this reason, both Iand Q-inputs must be externally driven for the DESCLKIQ Mode. The DCLK Bit (Addr: Eh, Bit 6) is used to select the 180° sampling clock mode.

The DESCLKIQ Mode results in the best bandwidth for the interleaved modes. In general, the bandwidth decreases from Non-DES Mode to DES Mode (specifically, DESI or DESQ) because both channels are sampling off the same input signal and non-ideal effects introduced by interleaving the two channels lower the bandwidth. Driving both I- and Q-channels externally (DESIQ Mode and DESCLKIQ Mode) results in better bandwidth for the DES Mode because each channel is being driven, which reduces routing losses. The DESCLKIQ Mode has better bandwidth than the DESIQ Mode because the routing internal to the ADC12D1800RF is simpler, which results in less insertion loss. PLEASE NOTE: Due to the electrical separation of the I and Q signal paths in the DESCLKIQ mode the SFDR performance in this mode will be significantly worse than in any of the other DES modes. For this reason this mode is only recommended for applications where input bandwidth is more important than spurious performance.

In the DES Mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If the device is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If the sampling clock is 1.8 GHz, the effective sampling rate is doubled to 3.6 GSPS and each of the 4 output buses has an output rate of 900 MSPS. All data is available in parallel. To properly reconstruct the sampled waveform, the four bytes of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See Figure 4-2. If the device is programmed into the Non-Demux DES Mode, two bytes of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI. See Figure 4-5.

5.4.2 Demux/Non-Demux Mode

he ADC12D1800RF may be in one of two demultiplex modes: Demux Mode or Non-Demux Mode (also sometimes referred to as 1:1 Demux Mode). In Non-Demux Mode, the data from the input is simply output at the sampling rate on one 12-bit bus. In Demux Mode, the data from the input is output at half the sampling rate, on twice the number of buses. Demux/Non-Demux Mode may only be selected by the NDM pin; see Section 5.5.1.1.2. In Non-DES Mode, the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES Mode) or not demultiplexed (Non-Demux Non-DES Mode). In DES Mode, the output data from both channels interleaved may be demultiplexed (1:4 Demux DES Mode) or not demultiplexed (Non-Demux DES Mode). Note that for Non-Demux Mode, 90° DDR Mode and SDR Mode are not available. See Table 5-5 for a selection of available modes.

Table 5-5 Supported Demux, Data Rate Modes

Non-Demux Mode 1:2 Demux Mode
DDR 0° Mode Only 0° Mode / 90° Mode
SDR Not Available Rising / Falling Mode

5.5 Programming

5.5.1 Control Modes

The ADC12D1800RF may be operated in one of two control modes: Non-extended Control Mode (Non-ECM) or Extended Control Mode (ECM). In the simpler Non-ECM (also sometimes referred to as Pin Control Mode), the user affects available configuration and control of the device through the control pins. The ECM provides additional configuration and control options through a serial interface and a set of 16 registers, most of which are available to the customer.

5.5.1.1 Non-Extended Control Mode

In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are controlled via various pin settings. Non-ECM is selected by setting the ECE Pin to logic-high. Note that, for the control pins, "logic-high" and "logic-low" refer to VA and GND, respectively. Nine dedicated control pins provide a wide range of control for the ADC12D1800RF and facilitate its operation. These control pins provide DES Mode selection, Demux Mode selection, DDR Phase selection, execute Calibration, Calibration Delay setting, Power Down I-channel, Power Down Q-channel, Test Pattern Mode selection, and Full-Scale Input Range selection. In addition to this, two dual-purpose control pins provide for AC/DC-coupled Mode selection and LVDS output common-mode voltage selection. See Table 5-6 for a summary.

Table 5-6 Non-ECM Pin Summary

Pin Name Logic-Low Logic-High Floating
Dedicated Control Pins
DES Non-DES Mode DES
Mode
Not valid
NDM Demux
Mode
Non-Demux Mode Not valid
DDRPh 0° Mode 90° Mode Not valid
CAL See Section 5.5.1.1.4 Not valid
CalDly Shorter delay Longer delay Not valid
PDI I-channel active Power Down
I-channel
Power Down
I-channel
PDQ Q-channel active Power Down
Q-channel
Power Down
Q-channel
TPM Non-Test Pattern Mode Test Pattern Mode Not valid
FSR Not allowed Nominal FS input Range Not valid
Dual-purpose Control Pins
VCMO AC-coupled operation Not allowed DC-coupled operation
VBG Not allowed Higher LVDS common-mode voltage Lower LVDS common-mode voltage

5.5.1.1.1 Dual Edge Sampling Pin (DES)

The Dual Edge Sampling (DES) Pin selects whether the ADC12D1800RF is in DES Mode (logic-high) or Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a time-interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In Non-ECM, only the I-input may be used for DES Mode, a.k.a. "DESI Mode". In ECM, the Q-input may be selected via the DEQ Bit (Addr: 0h, Bit: 6), a.k.a. "DESQ Mode". In ECM, both the I- and Q-inputs maybe selected, a.k.a. "DESIQ Mode".

To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See Section 5.4.1 for more information.

5.5.1.1.2 Non-Demultiplexed Mode Pin (NDM)

The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1800RF is in Demux Mode (logic-low) or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the sampled rate at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the sampled rate at twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce its data on one or two buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected channel will produce its data on two or four buses for Non-Demux or Demux Mode, respectively.

This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Section 5.4.2 for more information.

5.5.1.1.3 Dual Data Rate Phase Pin (DDRPh)

The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1800RF is in 0° Mode (logic-low) or 90° Mode (logic-high) for DDR Mode. If the device is in SDR Mode, then the DDRPh Pin selects whether the ADC12D1800RF is in Falling Mode (logic low) or Rising Mode (logic high). For DDR Mode, the Data may transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode). The DDRPh Pin selects 0° Mode or 90° Mode for both the I-channel: DI- and DId-to-DCLKI phase relationship and for the Q-channel: DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See Section 5.3.2.1 for more information.

5.5.1.1.4 Calibration Pin (CAL)

The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power-on will prevent execution of the power-on calibration. In ECM, this pin remains active and is logically OR'd with the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Section 5.3.3 for more information.

5.5.1.1.5 Calibration Delay Pin (CalDly)

The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the application of power, until the start of the power-on calibration. The actual delay time is specified as tCalDly and may be found in Section 4.15. This feature is pin-controlled only and remains active in ECM. It is recommended to select the desired delay time prior to power-on and not dynamically alter this selection.

See Section 5.3.3 for more information.

5.5.1.1.6 Power Down I-channel Pin (PDI)

The Power Down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active (logic-low). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will contain meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I-channel powered down or active and may be found in Section 4.12. The device should be recalibrated following a power-cycle of PDI (or PDQ).

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used to power-down the I-channel. See Section 5.3.4 for more information.

5.5.1.1.7 Power Down Q-channel Pin (PDQ)

The Power Down Q-channel (PDQ) Pin selects whether the Q-channel is powered down (logic-high) or active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q-channel. The PDI and PDQ pins function independently of each other to control whether each I- or Q-channel is powered down or active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be used to power-down the Q-channel. See Section 5.3.4 for more information.

5.5.1.1.8 Test Pattern Mode Pin (TPM)

The Test Pattern Mode (TPM) Pin selects whether the output of the ADC12D1800RF is a test pattern (logic-high) or the converted analog input (logic-low). The ADC12D1800RF can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In TPM, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. See Section 5.3.2.5 for more information.

5.5.1.1.9 Full-Scale Input Range Pin (FSR)

The Full-Scale Input Range (FSR) Pin sets the full-scale input range for both the I- and Q-channel; for the ADC12D1800RF, only the logic-high setting is available. The input full-scale range is specified as VIN_FSR in Section 4.7. In Non-ECM, the full-scale input range for each I- and Q-channel may not be set independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to obtain optimal performance.

To use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh). See Section 5.3.1 for more information.

5.5.1.1.10 AC / DC-Coupled Mode Pin (VCMO)

The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and Non-ECM.

5.5.1.1.11 LVDS Output Common-mode Pin (VBG)

The VBG Pin serves a dual purpose. When functioning as an output, it provides the bandgap reference. When functioning as an input, it selects whether the LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be found in Section 4.11. This pin is always active, in both ECM and Non-ECM.

5.5.1.2 Extended Control Mode

In Extended Control Mode (ECM), most functions are controlled via the Serial Interface. In addition to this, several of the control pins remain active. See Table 5-1 for details. ECM is selected by setting the ECE Pin to logic-low. If the ECE Pin is set to logic-high (Non-ECM), then the registers are reset to their default values. So, a simple way to reset the registers is by toggling the ECE pin. Four pins on the ADC12D1800RF control the Serial Interface: SCS, SCLK, SDI and SDO. This section covers the Serial Interface. The Register Definitions are located at the end of the datasheet so that they are easy to find, see Section 5.6.1.

5.5.1.2.1 The Serial Interface

The ADC12D1800RF offers a Serial Interface that allows access to the sixteen control registers within the device. The Serial Interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in his system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 5-7. See Figure 4-8 for the timing diagram and Section 4.14 for timing specification details. Control register contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and SCS pins may be left floating because they each have an internal pull-up.

Table 5-7 Serial Interface Pins

Pin Name
C4 SCS (Serial Chip Select bar)
C5 SCLK (Serial Clock)
B4 SDI (Serial Data In)
A3 SDO (Serial Data Out)

SCS: Each assertion (logic-low) of this signal starts a new register access, i.e. the SDI command field must be ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the 24th clock, no data read / write will occur. For a read operation, if the SCS is asserted longer than 24 clocks, the SDO output will hold the D0 bit until SCS is de-asserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write will occur normally through the SDI input upon the 24th clock. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed. SCS must be toggled in between register access cycles.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see fSCLK in Section 4.14 for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. If the SDI and SDO wired are shared (3-wire mode), then during read operations it is necessary to tri-state the master which is driving SDI while the data field is being output by the ADC on SDO. The master must be at TRI-STATE before the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed.

SDO: This output is normally at TRI-STATE and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th clock's falling edge. At the end of the access, when SCS is de-asserted, this output is at TRI-STATE once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there will be a bus turnaround time, tBSU, from when the last bit of the command field was read in until the first bit of the data field is written out.

Table 5-8 shows the Serial Interface bit definitions.

Table 5-8 Command and Data Field Definitions(1)

Bit No. Name Comments
1 Read / Write (R/W) 1b indicates a read operation
0b indicates a write operation
2-3 Reserved Bits must be set to 10b
4-7 A<3:0> 16 registers may be addressed. The order is MSB first
8 X This is a "don't care" bit
9-24 D<15:0> Data written to or read from addressed register
(1) The serial data protocol is shown for a read and write operation in Figure 5-5 and Figure 5-6, respectively.
ADC12D1800RF 30164392.gifFigure 5-5 Serial Data Protocol - Read Operation
ADC12D1800RF 30164393.gifFigure 5-6 Serial Data Protocol - Write Operation

5.6 Register Maps

5.6.1 Register Definitions

Twelve read / write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. See Table 5-9 for a summary. For a description of the functionality and timing to read / write the control registers, see Section 5.5.1.2.1.

NOTE

Register 6h must be written to 1C0Eh for the device to perform at full rated performance for Fclk > 1.6GHz.

Table 5-9 Register Addresses

A3 A2 A1 A0 Hex Register Addressed
0 0 0 0 0h Configuration Register 1
0 0 0 1 1h Reserved
0 0 1 0 2h I-channel Offset
0 0 1 1 3h I-channel Full-Scale Range
0 1 0 0 4h Calibration Adjust
0 1 0 1 5h Calibration Values
0 1 1 0 6h Bias Adjust
0 1 1 1 7h DES Timing Adjust
1 0 0 0 8h Reserved
1 0 0 1 9h Reserved
1 0 1 0 Ah Q-channel Offset
1 0 1 1 Bh Q-channel Full-Scale Range
1 1 0 0 Ch Aperture Delay Coarse Adjust
1 1 0 1 Dh Aperture Delay Fine Adjust
1 1 1 0 Eh AutoSync
1 1 1 1 Fh Reserved

Table 5-10 Configuration Register 1

Addr: 0h (0000b) POR state: 2000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE SDR Res
POR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration.(1)
Bit 14 DPS: DCLK Phase Select. In DDR Mode, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the 90° Mode. In SDR Mode, set this bit to 0b to transition the data on the Rising edge of DCLK; set this bit to 1b to transition the data on the Falling edge of DCLK.
Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Section 4.11 for details.
Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog inputs. See Section 5.3.2.5 for details about the TPM pattern.
Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even in ECM.
Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is active, even in ECM.
Bit 9 Reserved. Must be set to 0b.
Bit 8 LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1b for improved performance.
Bit 7 DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set to 1b, the device will operate in the DES Mode. See Section 5.4.1 for more information.
Bit 6 DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the device will operate on. The default setting of 0b selects the I-input and 1b selects the Q-input.
Bit 5 DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1b shorts the I- and Q-inputs internally to the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. To operate the device in DESIQ Mode, Bits<7:5> must be set to 101b. In this mode, both the I- and Q-inputs must be externally driven; see Section 5.4.1 for more information.
The allowed DES Modes settings are shown below: For DESCLKIQ Mode, see Addr Eh.
Mode Addr 0h, Bits<7:5> Addr Eh, Bit<6>
Non-DES Mode 000b 0b
DESI Mode 100b 0b
DESQ Mode 110b 0b
DESIQ Mode 101b 0b
DESCLKIQ Mode 000b 1b
Bit 4 2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set to 1b, the data is output in Two's Complement format.(1)
Bit 3 TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the feature is enabled. See Section 5.3.2 for more information about this feature.
Bit 2 SDR: Single Data Rate. For the default setting of 0b, the data is clocked in Dual Data Rate; when set to 1b, the data is clocked in Single Data Rate. See Section 5.3.2 for more information about this feature. Note that for Non-Demux Mode, only 0° DDR Mode is available. See Table 5-5 for a selection of available modes.
Bits 1:0 Reserved. Must be set as shown.
(1) This pin / bit functionality is not tested in production test; performance is tested in the specified / default mode only.

Table 5-11 Reserved

Addr: 1h (0001b) POR state: 2907h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res
POR 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1
Bits 15:0 Reserved. Must be set as shown.

Table 5-12 I-channel Offset Adjust

Addr: 2h (0010b) POR state: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res OS OM(11:0)
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs.
Code Offset [mV]
0000 0000 0000 (default) 0
1000 0000 0000 22.5
1111 1111 1111 45

Table 5-13 I-channel Full Scale Range Adjust

Addr: 3h (0011b) POR state: 4000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res FM(14:0)
POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The allowable range is from 800 mV (16384d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. A greater range of FSR values is available in ECM, i.e. FSR values above 800 mV. See VIN_FSR in Section 4.7 for characterization details.
Code FSR [mV]
100 0000 0000 0000 (default) 800
111 1111 1111 1111 1000

Table 5-14 Calibration Adjust(1)

Addr: 4h (0100b) POR state: DB4Bh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res CSS Res SSC Res
POR 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1
(1) This feature functionality is not tested in production test; performance is tested in the specified / default mode only.
Bit 15 Reserved. Must be set as shown.
Bit 14 CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity Calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity Calibration).
Bits 13:8 Reserved. Must be set as shown.
Bit 7 SSC: SPI Scan Control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read / written. When not reading / writing the calibration values, this control bit should left at its default 0b setting. See Section 5.3.3 for more information.
Bits 6:0 Reserved. Must be set as shown.

Table 5-15 Calibration Values(1)

Addr: 5h (0101b) POR state: XXXXh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SS(15:0)
POR X X X X X X X X X X X X X X X X
(1) This feature functionality is not tested in production test; performance is tested in the specified / default mode only.
Bits 15:0 SS(15:0): SPI Scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may be read from/ written to it. Set SSC (Addr: 4h, Bit 7) to read / write. See Section 5.3.3 for more information.

Table 5-16 Bias Adjust

Addr: 6h (0110b) POR state: 1C2Eh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MPA(15:0)
POR 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0
Bits 15:0 MPA(15:0): Max Power Adjust. This register must be written to 1C0Eh to achieve full rated performance for Fclk > 1.6GHz.

Table 5-17 DES Timing Adjust

Addr: 7h (0111b) POR state: 8142h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DTA(6:0) Res
POR 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0
Bits 15:9 DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Section 5.3.1 for more information. The nominal step size is 30fs.
Bits 8:0 Reserved. Must be set as shown.

Table 5-18 Reserved

Addr: 8h (1000b) POR state: 0F0Fh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res
POR 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bits 15:0 Reserved. Must be set as shown.

Table 5-19 Reserved

Addr: 9h (1001b) POR state: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:0 Reserved. Must be set as shown.

Table 5-20 Q-channel Offset Adjust

Addr: Ah (1010b) POR state: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res OS OM(11:0)
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs.
Code Offset [mV]
0000 0000 0000 (default) 0
1000 0000 0000 22.5
1111 1111 1111 45

Table 5-21 Q-channel Full-Scale Range Adjust

Addr: Bh (1011b) POR state: 4000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res FM(14:0)
POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The allowable range is from 800 mV (16384d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. A greater range of FSR values is available in ECM, i.e. FSR values above 800 mV. See VIN_FSR in Section 4.7 for characterization details.
Code FSR [mV]
100 0000 0000 0000 (default) 800
111 1111 1111 1111 1000

Table 5-22 Aperture Delay Coarse Adjust

Addr: Ch (1100b) POR state: 0004h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CAM(11:0) STA DCC Res
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Aperture Delay Adjust feature cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) for CLK frequencies above 1600 MHz.

Using the tAD Adjust feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.

Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function.
Bit 3 STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which will make both coarse and fine adjustment settings, i.e. CAM(11:0) and FAM(5:0), available.
Bit 2 DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature is enabled by default.
Bits 1:0 Reserved. Must be set to 0b.

Table 5-23 Aperture Delay Fine Adjust(1)

Addr: Dh (1101b) POR state: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FAM(5:0) Res Res
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(1) This feature functionality is not tested in production test; performance is tested in the specified / default mode only.

Aperture Delay Adjust feature cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) for CLK frequencies above 1600 MHz.

Using the tAD Adjust feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.

Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bits 9:0 Reserved. Must be set as shown.

Table 5-24 AutoSync

Addr: Eh (1110b) POR state: 0003h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRC(8:0) DCK Res SP(1:0) ES DOC DR
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15:7 DRC(8:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1200 ps (319d). The delay remains the maximum of 1200 ps for any codes above or equal to 639d. See Section 6.1.4 for more information.
Bit 6 DCK: DESCLKIQ Mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I- and Q-channels 180° out of phase with respect to one another, i.e. the DESCLKIQ Mode. To select the DESCLKIQ Mode, Addr: 0h, Bits<7:5> must also be set to 000b. See Section 5.4.1 for more information.
Bit 5 Reserved. Must be set as shown.
Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2 ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this bit is set to 0b, then the device is in Master Mode.
Bit 1 DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in Master or Slave Mode, as determined by ES (Bit 2).
Bit 0 DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality.

Table 5-25 Reserved

Addr: Fh (1111b) POR state: 001Dh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Res
POR 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Bits 15:0 Reserved. This address is read only.