SNAS333E August   2005  – December 2015 ADC128S052 , ADC128S052-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Commercial
    3. 6.3 ESD Ratings - Automotive
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
      2. 7.3.2 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Digital Inputs and Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequence
    2. 9.2 Power Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Specification Definitions
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
ADC128S052 ADC128S052-Q1 20162605.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 CS Digital I/O Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low.
2 VA Power Supply Positive analog supply pin. This voltage is also used as the reference voltage. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.
3 AGND Power Supply The ground return for the analog supply and signals.
4 IN0 to IN7 Analog I/O Analog inputs. These signals can range from 0 V to VREF.
5
6
7
8
9
10
11
12 DGND Power Supply The ground return for the digital supply and signals.
13 VD Power Supply Positive digital supply pin. This pin must be connected to a 2.7-V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.
14 DIN Digital I/O Digital data input. The control register of the ADC128S052 is loaded through this pin on rising edges of the SCLK pin.
15 DOUT Digital I/O Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
16 SCLK Digital I/O Digital clock input. The ensured performance range of frequencies for this input is
3.2 MHz to 8 MHz. This clock directly controls the conversion and readout processes.