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DSP type 1 C64x DSP (max) (MHz) 720, 800, 900, 1100 CPU 32-/64-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 720, 800, 900, 1100 CPU 32-/64-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (CUT) 529 361 mm² 19 x 19 FCBGA (ZUT) 529 361 mm² 19 x 19
  • High-Performance Digital Media Processor
    • 720-MHz, 800-MHz, 900-MHz, 1.1-GHz C64x+™ Clock Rates
    • 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), 0.91 ns (-1100) Instruction Cycle Time
    • 5760, 6400, 7200, 8800 MIPS
    • Eight 32-Bit C64x+ Instructions/Cycle
    • Fully Software-Compatible With C64x/Debug
    • Commercial Temperature Ranges (-720, -900, and -1100 only)
    • Extended Temperature Ranges (-800 only)
    • Industrial Temperature Ranges (-720, -900, and -1100 only)
  • VelociTI.2™ Extensions to VelociTI™
    Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-bit Data)
    • 8-bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-bit (32K-byte) L1P Program RAM/Cache [Direct Mapped]
    • 256K-bit (32K-byte) L1D Data RAM/Cache
      [2-Way Set-Associative]
    • 2M-bit/256K-byte (DM647) or 4M-Bit/512K-byte) (DM648) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Five Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions/Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit Wide EMIF (EMIFA)
      • Up to 128M-Byte Total Address Reach
      • 64M-Byte Address Reach per CE Space
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
    • Synchronous Memories (SBSRAM and ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 3-Port Gigabit Ethernet Switch Subsystem
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One UART (With RTS and CTS Flow Control)
  • One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Audio Serial Port (McASP)
    • Ten Serializers and SPDIF (DIT) Mode
  • 16/32-Bit Host-Port Interface (HPI)
  • Advanced Event Triggering (AET) Compatible
  • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
  • VLYNQ™ Interface (FPGA Interface)
  • On-Chip ROM Bootloader
  • Individual Power-Saving Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Package:
    • 529-pin nFBGA (ZUT suffix)
    • 19x19 mm 0.8 mm pitch BGA
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -900, -1100)
  • High-Performance Digital Media Processor
    • 720-MHz, 800-MHz, 900-MHz, 1.1-GHz C64x+™ Clock Rates
    • 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), 0.91 ns (-1100) Instruction Cycle Time
    • 5760, 6400, 7200, 8800 MIPS
    • Eight 32-Bit C64x+ Instructions/Cycle
    • Fully Software-Compatible With C64x/Debug
    • Commercial Temperature Ranges (-720, -900, and -1100 only)
    • Extended Temperature Ranges (-800 only)
    • Industrial Temperature Ranges (-720, -900, and -1100 only)
  • VelociTI.2™ Extensions to VelociTI™
    Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-bit Data)
    • 8-bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-bit (32K-byte) L1P Program RAM/Cache [Direct Mapped]
    • 256K-bit (32K-byte) L1D Data RAM/Cache
      [2-Way Set-Associative]
    • 2M-bit/256K-byte (DM647) or 4M-Bit/512K-byte) (DM648) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Five Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions/Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit Wide EMIF (EMIFA)
      • Up to 128M-Byte Total Address Reach
      • 64M-Byte Address Reach per CE Space
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
    • Synchronous Memories (SBSRAM and ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 3-Port Gigabit Ethernet Switch Subsystem
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One UART (With RTS and CTS Flow Control)
  • One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Audio Serial Port (McASP)
    • Ten Serializers and SPDIF (DIT) Mode
  • 16/32-Bit Host-Port Interface (HPI)
  • Advanced Event Triggering (AET) Compatible
  • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
  • VLYNQ™ Interface (FPGA Interface)
  • On-Chip ROM Bootloader
  • Individual Power-Saving Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Package:
    • 529-pin nFBGA (ZUT suffix)
    • 19x19 mm 0.8 mm pitch BGA
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -900, -1100)

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the C64x+ DSP, see the (literature number SPRU732).

The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the video port peripherals, see the (literature number SPRUEM1).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the C64x+ DSP, see the (literature number SPRU732).

The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the video port peripherals, see the (literature number SPRUEM1).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320DM647/TMS320DM648 Digital Media Processors 数据表 (Rev. H) 2012年 4月 10日
* 勘误表 TMS320DM647, TMS320DM648 Digital Media Processors Silicon Errata (Rev. G) 2011年 11月 1日
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port UG (Rev. B) 2010年 11月 12日
应用手册 TMS320DM647/8 Power Consumption Summary (Rev. B) 2010年 1月 6日
应用手册 Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 2009年 9月 24日
用户指南 TMS320DM647/DM648 DSP 3 Port Switch Ethernet Subsystem User's Guide (Rev. B) 2009年 7月 14日
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
应用手册 TMS320DM648/7 SoC Architecture and Throughput Overview 2009年 6月 12日
应用手册 Using the TMS320DM647/DM648 Bootloader (Rev. D) 2009年 6月 1日
用户指南 TMS320DM647/DM648 DSP Subsystem User's Guide (Rev. B) 2009年 4月 24日
用户指南 TMS320DM647DM648 DSP 64-Bit Timer User's Guide (Rev. B) 2009年 3月 10日
用户指南 TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide (Rev. B) 2008年 11月 11日
更多文献资料 End-to-end video infrastructure solutions 2008年 8月 29日
应用手册 Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008年 8月 21日
应用手册 Migrating from TMS320DM642 to TMS320DM648/DM6437 2008年 8月 19日
更多文献资料 达芬奇技术概述手册 (Rev. B) 英语版 (Rev.B) 2008年 8月 12日
应用手册 Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日
用户指南 TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (Rev. B) 2008年 2月 16日
用户指南 TMS320DM647/DM648 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B) 2007年 12月 8日
用户指南 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide (Rev. A) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. B) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. A) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP Serial Peripheral Interface (SPI) User’s Guide (Rev. A) 2007年 10月 2日
用户指南 TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 2007年 10月 2日
更多文献资料 DaVinci Newsletter - Fall 2007 Issue (Rev. B) 2007年 8月 14日
用户指南 MPEG2 Main Profile Decoder on C64x+ (on DRA446 –Low Memory configuration) UG 2007年 7月 31日
应用手册 Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 2007年 6月 7日
用户指南 TMS320DM647/DM648 DSP VLYNQ Port User's Guide 2007年 6月 5日
应用手册 Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007年 5月 20日

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调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

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TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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应用软件和框架

TMDMFP — 多媒体框架产品 (MFP) - 编解码器引擎,框架组件和 xDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable DSPs over fixed-function devices is their ability to accelerate multiple multimedia functions in a single device. TI multimedia framework products are designed to enable users to easily share a DSP between algorithms by handling (...)

用户指南: PDF
驱动程序或库

NDKTCPIP — TI-RTOS 网络

TI-RTOS Networking(以前称为 NDK 或网络开发者套件)将双模式 IPv4/IPv6 堆栈与一些网络应用结合在一起。作为 TI-RTOS 的一部分,TI-RTOS Networking 支持适用于支持以太网的 MCU 以及基于高性能 TMS320C6000™ DSP 的器件。
用户指南: PDF
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
驱动程序或库

SPRC542 — C64x+ IQMath 库 - 虚拟浮点引擎

Texas Instruments TMS320C64x+ IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C64x+ devices. These routines are typically used in computationally (...)
用户指南: PDF
驱动程序或库

SPRC831 — 视频影像协处理器 (VICP) 信号处理库

德州仪器 (TI) VICP 信号处理库是高度优化的软件算法的集合,它在 VICP 硬件加速器上运行。该库使应用开发人员能够有效地利用 VICP 性能,而无需将宝贵时间花在开发用于加速器的软件上。具有成熟的可用性和性能优化算法,VICP 信号处理库能够显著降低应用开发时间。DSP 上的自由 MIPS 使应用开发人员能够将更多差异化功能包含在最终应用中。

VICP 硬件加速器是一个并行 MAC 引擎。通过执行各种计算密集型任务,该加速器能够非常有效地提高 DSP 的性能,这完全归功于它的灵活架构。

VICP 支持各种算法以便能提供其它 DSP 资源
  • 矩阵运算/阵列运算:
    • (...)
用户指南: PDF
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
软件编解码器

DM648CODECS 用于 DM648 和 DM647 器件的编解码器

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into your application. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on that page, (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320DM647 数字媒体处理器 TMS320DM648 数字媒体处理器
下载选项
仿真模型

DM647/DM648 ZUT BSDL Model (Rev. A)

SPRM256A.ZIP (11 KB) - BSDL Model
仿真模型

DM647/DM648 ZUT BSDL version 1.1 Model

SPRM361.ZIP (11 KB) - BSDL Model
仿真模型

DM647/DM648 ZUT IBIS Model (Rev. A)

SPRM257A.ZIP (886 KB) - IBIS Model
封装 引脚 CAD 符号、封装和 3D 模型
FCBGA (CUT) 529 Ultra Librarian
FCBGA (ZUT) 529 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频