ZHCSE92 September   2015 INA188

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    6. 6.6 Electrical Characteristics: VS = ±2 V to < ±4 V (VS = 4 V to < 8 V)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inside the INA188
      2. 7.3.2 Setting the Gain
        1. 7.3.2.1 Gain Drift
      3. 7.3.3 Zero Drift Topology
        1. 7.3.3.1 Internal Offset Correction
        2. 7.3.3.2 Noise Performance
        3. 7.3.3.3 Input Bias Current Clock Feedthrough
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Input Protection and Electrical Overstress
      6. 7.3.6 Input Common-Mode Range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
      2. 7.4.2 Offset Trimming
      3. 7.4.3 Input Bias Current Return Path
      4. 7.4.4 Driving the Reference Pin
      5. 7.4.5 Error Sources Example
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The INA188 measures a small differential voltage with a high common-mode voltage developed between the noninverting and inverting input. The low offset drift in conjunction with no 1/f noise makes the INA188 suitable for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations.

8.2 Typical Application

Figure 55 shows the basic connections required for operating the INA188. Applications with noisy or high-impedance power supplies may require decoupling capacitors close to the device pins. The output is referred to the output reference (REF) pin that is normally grounded. The reference pin must be a low-impedance connection to assure good common-mode rejection.

INA188 ai_plc_input_sbos632.gif Figure 55. PLC Input (±10 V, 4 mA to 20 mA)

8.2.1 Design Requirements

For this application, the design requirements are:

  • 4-mA to 20-mA input with less than 20-Ω burden
  • ±20-mA input with less than 20-Ω burden
  • ±10-V input with impedance of approximately 100 kΩ
  • Maximum 4-mA to 20-mA or ±20mA burden voltage equal to ±0.4 V
  • Output range within 0 V to 5 V

8.2.2 Detailed Design Procedure

The following steps must be applied for proper device functionality:

  • For a 4-mA to 20-mA input, the maximum burden of 0.4 V must have a burden resistor equal to 0.4 / 0.02 = 20 Ω.
  • To center the output within the 0-V to 5-V range, VREF must equal 2.5 V.
  • To keep the ±20-mA input linear within 0 V to 5 V, the gain resistor (RG) must be 12.4 kΩ.
  • To keep the ±10-V input within the 0-V to 5-V range, attenuation must be greater than 0.05.
  • A 100-kΩ resistor in series with a 4.87-kΩ resistor provides 0.0466 attenuation of ±10 V, well within the ±2.5-V linear limits.

8.2.3 Application Curve

INA188 D326_SBOS632.gif Figure 56. Plot of PLC Input Transfer Function