CDCVF2505 具有扩频兼容性和断电模式的 PLL 时钟驱动器,用于 SDRAM 以及通用应用领域 | 德州仪器

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具有扩频兼容性和断电模式的 PLL 时钟驱动器,用于 SDRAM 以及通用应用领域

具有扩频兼容性和断电模式的 PLL 时钟驱动器,用于 SDRAM 以及通用应用领域 - CDCVF2505


The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.

The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.


  • Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)
  • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin TSSOP and 8-Pin SOIC Packages
  • Consumes Less Than 100 mA (Typical) in Power-Down Mode
  • Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
  • 25-Ω On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the Need for External Components


与其它产品相比 时钟缓冲器 邮件 下载到电子表格中
Part number 立即下单 Function Output frequency (Max) (MHz) Number of outputs VCC core (V) Output skew (ps) Features Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG)
CDCVF2505 立即下单 Memory interface     200     4     3.3     150     SDR     -40 to 85     Catalog     LVCMOS     SOIC | 8
TSSOP | 8    
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)
8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)