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CDCV855

不推荐用于新设计

1:4 DDR pll 时钟驱动器

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CDCV855 不推荐用于新设计
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CDCVF855 正在供货 2.5V 锁相环路 DDR 时钟驱动器 Can achieve wider frequency ranges

CDCV855

不推荐用于新设计
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产品详情

Core supply voltage (V) 2.5 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog
Core supply voltage (V) 2.5 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (PW) 28 62.08 mm² 9.7 x 6.4
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Four Differential Clock Outputs
  • Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
  • Operates From Dual 2.5-V Supplies
  • 28-Pin TSSOP Package
  • Consumes < 200-µA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Four Differential Clock Outputs
  • Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
  • Operates From Dual 2.5-V Supplies
  • 28-Pin TSSOP Package
  • Consumes < 200-µA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.
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类型 标题 下载最新的英语版本 日期
* 数据表 2.5-V Phase-Lock Loop Clock Driver 数据表 (Rev. A) 2002年 12月 12日
应用手册 Design Considerations for TI's CDCV857/CDCV857A/CDCV855 DRR PLL (Rev. A) 2005年 11月 20日
应用手册 Design Considerations for TI's CDCV857/CDCV857A DRR PLL 2002年 1月 10日

设计和开发

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仿真模型

CDCV855 IBIS Model (Rev. A)

SCAM026A.ZIP (9 KB) - IBIS Model
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TSSOP (PW) 28 查看选项
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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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