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CDC337

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具有三态输出的 1:8 CMOS 时钟驱动器

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CDC337

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Function Clock divider Output frequency (max) (MHz) 80 Number of outputs 8 Output supply voltage (V) 5 Core supply voltage (V) 5 Output skew (ps) 0.75 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
Function Clock divider Output frequency (max) (MHz) 80 Number of outputs 8 Output supply voltage (V) 5 Core supply voltage (V) 5 Output skew (ps) 0.75 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Distributes One Clock Input to Eight Outputs
    • Four Same-Frequency Outputs
    • Four Half-Frequency Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW)

    EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Distributes One Clock Input to Eight Outputs
    • Four Same-Frequency Outputs
    • Four Half-Frequency Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW)

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE\) input is low and the clear (CLR\) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR\ low asynchronously resets the Q outputs to the low level. When OE\ is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from -40°C to 85°C.

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE\) input is low and the clear (CLR\) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR\ low asynchronously resets the Q outputs to the low level. When OE\ is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from -40°C to 85°C.

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* 数据表 Clock Driver With 3-State Outputs 数据表 (Rev. B) 1998年 10月 27日

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