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  • TLV320ADC6120 2 通道、768kHz、Burr-BrownTM 音频 ADC

    • ZHCSMM9A December   2020  – June 2021 TLV320ADC6120

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  • TLV320ADC6120 2 通道、768kHz、Burr-BrownTM 音频 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 7.10 Timing Requirements: PDM Digital Microphone Interface
    11. 7.11 Switching Characteristics: PDM Digital Microphone Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Input Channel Configurations
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Programmable Microphone Bias
      6. 8.3.6  Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 8.3.7  Dynamic Range Enhancer (DRE)
      8. 8.3.8  Dynamic Range Compressor (DRC)
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Voice Activity Detection (VAD)
      11. 8.3.11 Digital PDM Microphone Record Channel
      12. 8.3.12 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 TLV320ADC6120 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

TLV320ADC6120 2 通道、768kHz、Burr-BrownTM 音频 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 多通道高性能 ADC：
    • 2 通道模拟麦克风输入或线路输入
    • 4 通道数字 PDM 麦克风
    • 多达 2 个模拟和多达 2 个数字麦克风通道
  • ADC 线路和麦克风差分输入性能：
    • 动态范围 (DR)：
      • 123dB，动态范围增强器 (DRE) 启用
      • 113dB，DRE 禁用
    • THD+N：-95dB
  • ADC 通道相加模式，DR 性能：
    • 116dB，DRE 禁用，2 通道相加
  • ADC 输入电压：
    • 差分 2VRMS 满量程输入
    • 单端 1VRMS 满量程输入
  • ADC 采样率 (fS) = 8kHz 至 768kHz
  • 可编程通道设置：
    • 通道增益：0dB 至 42dB，步长 0.5dB
    • 数字音量控制：–100dB 至 27dB
    • 增益校准分辨率为 0.1dB
    • 相位校准分辨率为 163ns
  • 可编程麦克风偏置或电源电压生成
  • 低延迟信号处理滤波器选择
  • 可编程 HPF 和双二阶数字滤波器
  • 自动增益控制器 (AGC)
  • 话音激活检测 (VAD)
  • I2C 控制接口
  • 集成高性能音频 PLL
  • 自动时钟分频器设置配置
  • 音频串行数据接口：
    • 格式：TDM、I2S 或左平衡 (LJ)
    • 字长：16 位、20 位、24 位或 32 位
    • 主/从接口
  • 单电源运行：3.3V 或 1.8V
  • I/O 电源运行：3.3V 或 1.8V
  • 1.8V AVDD 电源电压下的功耗：
    • 9.5mW/通道（48kHz 采样率）

2 应用

  • 智能扬声器
  • IP 网络摄像头
  • 专业麦克风和无线系统
  • 视频会议系统

3 说明

TLV320ADC6120 是一款高性能 Burr-Brown™ 音频模数转换器 (ADC)，最多可支持对脉冲密度调制 (PDM) 麦克风输入的两个模拟通道或四个数字通道进行同步采样。该器件支持线路和麦克风输入，并允许单端和差分输入配置。该器件集成了可编程通道增益、数字音量控制、可编程麦克风偏置电压、锁相环 (PLL)、可编程高通滤波器 (HPF)、双二阶滤波器、低延迟滤波器模式，并可实现高达 768kHz 的采样率，并可实现高达 192kHz 的采样率。该器件支持时分多路复用 (TDM)、I2S 或左平衡 (LJ) 音频格式，并可通过 I2C 接口进行控制。这些集成的高性能特性，以及采用 3.3V 或 1.8 V 单电源供电的功能，使该器件非常适用于远场麦克风录音应用中空间受限的音频系统。

TLV320ADC6120 的额定工作温度范围为 –40°C 至 +125°C，并且采用 20 引脚 WQFN 封装。

器件信息(1)
器件型号 封装 封装尺寸（标称值）
TLV320ADC6120 WQFN (20) 3.00mm × 3.00mm，间距为 0.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
GUID-39DB2572-2AE3-43FF-ABFF-2D22952D2F8E-low.gif简化版方框图

4 Revision History

Changes from Revision * (December 2020) to Revision A (June 2021)

  • 将文档状态从预告信息更改为量产数据Go

5 Device Comparison Table

FEATURE PCM1821 PCM1820 TLV320ADC3120 TLV320ADC5120 TLV320ADC6120
Control interface Pin control I2C
Digital audio serial interface TDM or I2S TDM or I2S or left-justified (LJ)
Audio analog channel 2 2 2 2 2
Digital microphone channel Not available (N/A) Not available (N/A) 4 4 4
Programmable MICBIAS voltage Not available (N/A) Not available (N/A) Yes Yes Yes
Dynamic range (DRE disabled) 106 dB 113 dB 106 dB 108 dB 113 dB
Dynamic range (DRE enabled) Not available (N/A) 123 dB Not available (N/A) 120 dB 123 dB
ADC SNR with DRE Not available (N/A) 123 dB Not available (N/A) 120 dB 123 dB
Input impedance 10 kΩ 2.5 kΩ 2.5 kΩ, 10 kΩ, 20 kΩ
Compatibility Pin-to-pin, package, drop-in replacements of each other Pin-to-pin, package, and control registers compatible; drop-in replacements of each other
Package WQFN (RTE), 20-pin, 3.00 mm × 3.00 mm (0.5-mm pitch)

6 Pin Configuration and Functions

GUID-61BFF8CC-EB03-45C6-9D31-24DB2A4022E0-low.gifFigure 6-1 RTE Package,20-Pin WQFN With Exposed Thermal Pad,Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 IN1P Analog input Analog input 1P pin.
2 IN1M Analog input Analog input 1M pin.
3 IN2P_GPI1 Analog input/digital input Analog input 2P pin or general-purpose digital input 1 (multipurpose functions such as digital microphones data, PLL input clock source, and so forth).
4 IN2M_GPO1 Analog input/digital output Analog input 2M pin or general-purpose digital output 1 (multipurpose functions such as digital microphone clock, interrupt, and so forth).
5 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
6 SDOUT Digital output Audio serial data interface bus output.
7 BCLK Digital I/O Audio serial data interface bus bit clock.
8 FSYNC Digital I/O Audio serial data interface bus frame synchronization signal.
9 IOVDD Digital supply Digital I/O power supply (1.8 V or 3.3 V, nominal).
10 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
11 GPIO1 Digital I/O General-purpose digital input/output 1 (multipurpose functions such as digital microphones clock or data, PLL input clock source, interrupt, and so forth).
12 SDA Digital I/O Data pin for I2C control bus.
13 SCL Digital input Clock pin for I2C control bus.
14 DREG Digital supply Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect a 10-µF and 0.1-µF low ESR capacitor in parallel to device ground (VSS).
15 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
16 AVDD Analog supply Analog power (1.8 V or 3.3 V, nominal).
17 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or external analog power (1.8 V, nominal). Connect a 10-µF and 0.1-µF low ESR capacitor in parallel to analog ground (AVSS).
18 VREF Analog Analog reference voltage filter output. Connect a 1-µF capacitor to analog ground (AVSS).
19 MICBIAS_GPI2 Analog output/digital input MICBIAS output or general-purpose digital input 2 (multipurpose functions such as digital microphones data, PLL input clock source, and so forth). If used as MICBIAS output, then connect a 1-µF capacitor to analog ground (AVSS).
20 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
Thermal Pad Thermal Pad (VSS) Ground supply Thermal pad shorted to internal device ground. Short the thermal pad directly to the board ground plane.

7 Specifications

 
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