ZHCSI26C August   2010  – April 2018 TPS54320

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与负载电流间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-up into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting UVLO
      10. 7.3.10 Slow Start (SS/TR)
      11. 7.3.11 Power Good (PWRGD)
      12. 7.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 7.3.13 Sequencing (SS/TR)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency and Synchronization (RT/CLK)
      2. 7.4.2 Adjustable Switching Frequency (RT Mode)
      3. 7.4.3 Synchronization (CLK Mode)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 文档支持
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

Layout Guidelines

Layout is a critical portion of good power supply design. See Figure 56 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and the PH node. Also on the top layer are connections for the remaining pins of the TPS54320 and a large top-side area filled with ground. The top layer ground area should be connected to the internal ground layer or layers using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS54320 device to provide a thermal path from the exposed thermal pad land to ground. The GND pin should be tied directly to the exposed thermal pad under the IC.

For operation at full-rated load, the top-side ground area together with the internal ground plane must provide adequate heat dissipating area. Several signals paths conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quiet analog ground trace rather than the power ground trace of the PVIN bypass capacitor.

Because the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout has been shown to produce good results and is meant as a guideline.

The estimated PCB area for the components used in the design of Figure 34 is 0.35 in2 (227 mm2). This area does not include test points or connectors.