ZHCSGL2E December   2016  – December 2023 LMK62A2-100M , LMK62A2-150M , LMK62A2-156M , LMK62A2-200M , LMK62A2-266M , LMK62E0-156M , LMK62E2-100M , LMK62E2-156M , LMK62I0-100M , LMK62I0-156M

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Supply
    6. 5.6  LVPECL Output Characteristics
    7. 5.7  LVDS Output Characteristics
    8. 5.8  HCSL Output Characteristics
    9. 5.9  OE Input Characteristics
    10. 5.10 Frequency Tolerance Characteristics
    11. 5.11 Power-On/Reset Characteristics (VDD)
    12. 5.12 PSRR Characteristics
    13. 5.13 PLL Clock Output Jitter Characteristics
    14. 5.14 Additional Reliability and Qualification
  7. Parameter Measurement Information
    1. 6.1 Device Output Configurations
  8. Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
        1. 7.2.1.1 Ensuring Thermal Reliability
        2. 7.2.1.2 Best Practices for Signal Integrity
        3. 7.2.1.3 Recommended Solder Reflow Profile
  9. Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Device Output Configurations

GUID-7B96702B-1550-476E-A388-8848FCCD6430-low.gifFigure 6-1 LVPECL Output DC Configuration During Device Test
GUID-49F8062C-F891-4E9B-BB65-D774C165A89D-low.gifFigure 6-2 LVDS Output DC Configuration During Device Test
GUID-AD31E356-F0DF-4D64-BD2A-6E797CCDBFA1-low.gifFigure 6-3 HCSL Output DC Configuration During Device Test (1)
GUID-0A68E8AD-D949-4F7B-9447-8FF8D4AB554D-low.gifFigure 6-4 LVPECL Output AC Configuration During Device Test
GUID-CF904018-56B5-4BE7-AD99-165454920D9B-low.gifFigure 6-5 LVDS Output AC Configuration During Device Test
GUID-867FE787-F16F-45E2-B593-68740F551707-low.gifFigure 6-6 HCSL Output AC Configuration During Device Test
GUID-F4DEF05C-B3CA-4D1F-8DD9-C73AACC1D6FB-low.gifFigure 6-7 PSRR Test Setup
GUID-36454F25-0DB0-4831-96B6-EE6DD573F1D1-low.gifFigure 6-8 Differential Output Voltage and Rise/Fall Time
Also compatible with 85 Ω termination