ISO782xLL 高性能 8000 VPK 增强型隔离式双 LVDS 缓冲器

器件信息⁽¹⁾

Pin Functions

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Power Ratings

6.6 Insulation Specifications

6.7 Safety-Related Certifications

6.8 Safety Limiting Values

6.9 DC Electrical Characteristics

6.10 DC Supply Current Characteristics

6.11 Switching Characteristics

6.12 Insulation Characteristics Curves

TA upto 150°C	Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS

Figure 1. Reinforced Isolation Capacitor Lifetime Projection for Devices in DW Package

Figure 3. Thermal Derating Curve for Limiting Current for DW Package

Figure 5. Thermal Derating Curve for Limiting Power for DW Package

TA upto 150°C	Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS

Figure 2. Reinforced Isolation Capacitor Lifetime Projection for Devices in DWW Package

Figure 4. Thermal Derating Curve for Limiting Current for DWW Package

Figure 6. Thermal Derating Curve for Limiting Power for DWW Package

6.13 Typical Characteristics

TA = 25°C

CH-A toggle

Figure 7. ISO7821LL Supply Current vs Data Rate (CH-A)

TA = 25°C

Figure 9. ISO7821LL Supply Current vs V_CCx Output Supply Voltage

Data rate = 100 Mbps

CH-B toggle

Figure 11. ISO7821LL Supply Current vs Temperature
(CH-B)

TA = 25°C

CH-B toggle

Figure 13. ISO7820LL Supply Current vs Data Rate
(CH-B)

Data rate = 100 Mbps

CH-A toggle

Figure 15. ISO7820LL Supply Current vs Temperature
(CH-A)

Figure 17. Propagation Delay Time vs Temperature

TA = 25°C

Figure 19. Output Voltage vs V_CCx Output Supply Voltage

Figure 21. Disable Time (t_PLZ, t_PHZ)

TA = 25°C

CH-B toggle

Figure 8. ISO7821LL Supply Current vs Data Rate (CH-B)

Data rate = 100 Mbps

CH-A toggle

Figure 10. ISO7821LL Supply Current vs Temperature
(CH-A)

TA = 25°C

CH-A toggle

Figure 12. ISO7820LL Supply Current vs Data Rate
(CH-A)

TA = 25°C

Figure 14. ISO7820LL Supply Current vs V_CCx Output Supply Voltage

Data rate = 100 Mbps

CH-B toggle

Figure 16. ISO7820LL Supply Current vs Temperature
(CH-B)

TA = 25°C

Figure 18. Propagation Delay Time vs V_CCx Output Supply Voltage

Figure 20. Disable to Enable Time (t_PZH, t_PZL)

8.1 Overview

The ISO782xLL is a family of isolated LVDS buffers. The differential signal received on the LVDS input pins is first converted to CMOS logic levels. The signal is then transmitted across a silicon-dioxide (SiO₂) based capacitive-isolation barrier using an on-off keying (OOK) modulation scheme. A high frequency carrier transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS outputs by a differential driver. These devices incorporate advanced circuit techniques to maximize CMTI performance and minimize radiated emissions.

The ISO782xLL family of devices is TIA/EIA-644-A standard compliant. The LVDS transmitters drive a minimum differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receivers are capable of detecting differential signals ≥50 mV in magnitude. The device consumes 10 mA per channel at 100 Mbps with 5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO782xLL family of devices.

8.2 Functional Block Diagram

8.3 Feature Description

The ISO782xLL family of devices is available in two channel configurations with a default differential high-output state.

8.4 Device Functional Modes

Table 1 lists the functional modes for the ISO782xLL family of devices.

8.4.1 Device I/O Schematics

Figure 28. Device I/O Schematics

9.1 Application Information

The ISO782xLL is a family of high-performance, reinforced isolated dual-LVDS buffers. Isolation can be used to help achieve human and system safety, to overcome ground potential difference (GPD), or to improve noise immunity and system performance.

The LVDS signaling can be used over most interfaces to achieve higher data rates because the LVDS is only a physical layer. LVDS can also be used for a proprietary communication scheme implemented between a host controller and a slave. Example use cases include connecting a high-speed I/O module to a host controller, a subsystem connecting to a backplane, and connection between two high-speed subsystems. Many of these systems operate under harsh environments making them susceptible to electromagnetic interferences, voltage surges, electrical fast transients (EFT), and other disturbances. These systems must also meet strict limits on radiated emissions. Using isolation in combination with a robust low-noise signaling standard such as LVDS, achieves both high immunity to noise and low emissions.

Example end applications that could benefit from the ISO782xLL family of devices include high-voltage motor control, test and measurement, industrial automation, and medical equipment.

9.2 Typical Application

One application for isolated LVDS buffers is for point-to-point communication between two high-speed capable, application-specific integrated circuits (ASICs) or FPGAs. In a high-voltage motor control application, for example, Node 1 could be a controller on a low-voltage or earth referenced board, and Node 2, could be controller placed on the power board, biased to high voltage. Figure 29 and Figure 30 show the application schematics.

Figure 30 provides further details of using the ISO782xLL family of devices to isolate the LVDS interface. The LVDS connection to the ISO782xLL family of devices can be traces on a board (shown as straight lines between Node 1 and the ISO782xLL device), a twisted pair cable (as shown between Node 2 and the ISO782xLL device), or any other controlled impedance channel. Differential 100-Ω terminations are placed near each LVDS receiver. The characteristic impedance of the channel should also be 100-Ω differential.

In the example shown in Figure 29 and Figure 30, the ISO782xLL family of devices provides reinforced or safety isolation between the high-voltage elements of the motor drive and the low-voltage control circuitry. This configuration also ensures reliable communication, regardless of the high conducted and radiated noise present in the system.

Figure 29. Isolated LVDS Interface in Motor Control Application

Figure 30. Isolated LVDS Interface Between Two Nodes (ASIC or FPGA)

9.2.2 Detailed Design Procedure

The ISO782xLL family of devices has minimum requirements on external components for correct operation. External bypass capacitors (0.1 µF) are required for both supplies (V_CC1 and V_CC2). A termination resistor with a value of 100 Ω is required between each differential input pair (INx+ and INx–), with the resistors placed as close to the device pins as possible. A differential termination resistor with a value of 100 Ω is required on the far end for the LVDS transmitters. Figure 31 and Figure 32 show these connections.

Figure 31. Typical ISO7820LL Circuit Hook-Up

Figure 32. Typical ISO7821LL Circuit Hook-Up

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO782xLL family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

9.2.3 Application Curve

Figure 33 shows a typical eye diagram of the ISO782xLL family of devices which indicates low jitter and a wide-open eye at the maximum data rate of 100 Mbps.

Figure 33. Eye Diagram at 100 Mbps PRBS, 3.3 V and 25°C