ISO782xLL 高性能 8000 VPK 增强型隔离式双 LVDS 缓冲器
- ZHCSFT4A March 2016 – August 2016 ISO7820LL , ISO7821LL
  
  PRODUCTION DATA.

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ISO782xLL 高性能 8000 VPK 增强型隔离式双 LVDS 缓冲器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合 TIA/EIA-644-A LVDS 标准
信号传输速率：高达 100Mbps
宽电源电压范围：2.25V 至 5.5V
宽环境温度范围：-55°C 至 +125°C
低功耗，100Mbps 时每通道的电流：
- 典型值 9.3mA (ISO7820LL)
- 典型值 9.5mA (ISO7821LL)
低传播延迟：17ns（典型值）
行业领先的 CMTI（最小值）：±100kV/μs
优异的电磁兼容性 (EMC)
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪涌保护
低辐射
隔离栅寿命：> 40 年
提供宽体和超宽体 SOIC-16 封装
可承受的隔离浪涌电压高达 12800 V_PK
安全相关认证：
- 符合 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 标准的 8000 V_PK
- 符合 UL 1577 标准且长达 1 分钟的 5700 V_RMS 隔离
- CSA 组件验收通知 5A，IEC 60950-1 和 IEC 60601-1 终端设备标准
- 符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证
- GB4943.1-2011 CQC 认证
- 已通过所有认证

2 应用

电机控制
测试和测量
工业自动化
医疗设备
通信系统

3 说明

ISO782xLL 系列器件是高性能隔离式双路 LVDS 缓冲器，隔离电压高达 8000V_PK。在隔离 LVDS 总线信号时，该器件可提供高电磁抗扰度，辐射较低，并且具有低功耗特性。每条隔离通道的 LVDS 接收和发送缓冲器均由二氧化硅 (SiO₂) 绝缘栅相隔离。

ISO7820LL 器件有两个正向通道。ISO7821LL 器件有一条正向通道和一条反向通道。

凭借创新型芯片设计和布线技术，ISO782xLL系列器件的电磁兼容性得到了显著增强，可缓解系统级 ESD、EFT 和浪涌问题并符合辐射标准。

ISO782xLL 系列器件提供 16 引脚 SOIC 宽体 (DW) 和超宽体 (DWW) 两种封装。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
ISO7820LL ISO7821LL	DW (16)	10.30mm x 7.50mm
ISO7820LL ISO7821LL	DWW (16)	10.30mm x 14.00mm

要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化电路原理图

V_CCI 和 GNDI 分别是输入通道的电源和接地连接。

V_CCO 和 GNDO 分别是输出通道的电源和接地连接。

4 修订历史记录

Changes from * Revision (March 2016) to A Revision

Changed 器件状态“产品预览”至“量产数据”并且已发布完整版本数据表Go

5 Pin Configuration and Functions

ISO7820LL DW and DWW Packages

16-Pin SOIC

Top View

ISO7820LL ISO7821LL po_iso7820ll_sllset8.gif

ISO7821LL DW and DWW Packages

16-Pin SOIC

Top View

ISO7820LL ISO7821LL po_iso7821llx_sllset5.gif

Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	ISO7820LL	ISO7821LL
EN1	—	7	I	Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high impedance state when EN1 is low.
EN2	10	10	I	Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high impedance state when EN2 is low.
GND1	2	2	—	Ground connection for V_CC1
GND1	8	8	—	Ground connection for V_CC1
GND2	9	9	—	Ground connection for V_CC2
GND2	15	15	—	Ground connection for V_CC2
INA+	3	3	I	Positive differential input, channel A
INA–	4	4	I	Negative differential input, channel A
INB+	6	11	I	Positive differential input, channel B
INB–	5	12	I	Negative differential input, channel B
NC	7	—	—	Not connected
OUTA+	14	14	O	Positive differential output, channel A
OUTA–	13	13	O	Negative differential output, channel A
OUTB+	11	6	O	Positive differential output, channel B
OUTB–	12	5	O	Negative differential output, channel B
V_CC1	1	1	—	Power supply, side 1, V_CC1
V_CC2	16	16	—	Power supply, side 2, V_CC2

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CCx	Supply voltage⁽²⁾	V_CC1, V_CC2	–0.5	6	V
V	Voltage on input, output, and enable pins	OUTx, INx, ENx	–0.5	V_CCx + 0.5⁽³⁾	V
I_O	Maximum current through OUTx pins		–20	20	mA
T_J	Junction temperature		–55	150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.25	3.3	5.5	V
\|V_ID\|	Magnitude of RX input differential voltage	Driven with voltage sources on RX pins	100		600	mV
V_IC	RX input common-mode voltage	V_CC1, V_CC2 ≥ 3 V	0.5 \|V_ID\|		2.4 – 0.5 \|V_ID\|	V
V_IC	RX input common-mode voltage	V_CC1, V_CC2 < 3 V	0.5 \|V_ID\|		V_CCx – 0.6 – 0.5 \|V_ID\|	V
R_L	TX far end differential termination			100		Ω
DR	Signaling rate		0		100	Mbps
T_A	Ambient temperature		–55	25	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO7820LL ISO7821LL		UNIT
		DW (SOIC)	DWW (SOIC)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	82	84.6	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	44.6	46.4	°C/W
R_θJB	Junction-to-board thermal resistance	46.6	55.3	°C/W
ψ_JT	Junction-to-top characterization parameter	17.8	18.7	°C/W
ψ_JB	Junction-to-board characterization parameter	46.1	54.5	°C/W
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	—	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 5 pF, input a 50-MHz 50% duty-cycle square wave, EN1 = EN2 = 5.5 V,
R_L = 100-Ω differential

PARAMETER		MAX	UNIT
ISO7821LL
P_D	Maximum power dissipation (both sides)	156	mW
P_D1	Maximum power dissipation (side 1)	78	mW
P_D2	Maximum power dissipation (side 2)	78	mW
ISO7820LL
P_D	Maximum power dissipation (both sides)	152	mW
P_D1	Maximum power dissipation (side 1)	36	mW
P_D2	Maximum power dissipation (side 2)	116	mW

6.6 Insulation Specifications

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	SPECIFICATION		UNIT
PARAMETER		TEST CONDITIONS	DW	DWW	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest terminal-to-terminal distance through air	>8	>14.5	mm
CPG	External creepage⁽¹⁾	Shortest terminal-to-terminal distance across the package surface	>8	>14.5	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	>21	>21	μm
CTI	Tracking resistance (comparative tracking index)	DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A	>600	>600	V
	Material group	According to IEC 60664-1	I	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 600 V_RMS	I–IV	I–IV
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 1000 V_RMS	I–III	I–IV
DIN V VDE V 0884–10 (VDE V 0884–10):2006–12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	AC voltage (bipolar)	2121	2828	V_PK
V_IOWM	Maximum isolation working voltage	AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; see Figure 1 and Figure 2	1500	2000	V_RMS
V_IOWM	Maximum isolation working voltage	DC voltage	2121	2828	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM t = 60 s (qualification) t = 1 s (100% production)	8000	8000	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 µs waveform, V_TEST = 1.6 × V_IOSM = 12800 V_PK (qualification)	8000	8000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.2 × V_IORM = 2545 V_PK (DW) and 3394 V_PK (DWW), t_m = 10 s	≤5	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.6 × V_IORM = 3394 V_PK (DW) and 4525 V_PK (DWW), t_m = 10 s	≤5	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IORM, t_ini = 1 s; V_pd(m) = 1.875 × V_IORM= 3977 V_PK (DW) and 5303 V_PK (DWW), t_m = 1 s	≤5	≤5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 × sin (2πft), f = 1 MHz	~0.7	~0.7	pF
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	>10¹²	>10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ 125°C	>10¹¹	>10¹¹
		V_IO = 500 V at T_S = 150°C	>10⁹	>10⁹
	Pollution degree		2	2
	Climatic category		55/125/21	55/125/21
UL 1577
V_ISO	Withstanding isolation voltage	V_TEST = V_ISO = 5700 V_RMS, t = 60 s (qualification); V_TEST = 1.2 × V_ISO = 6840 V_RMS, t = 1 s (100% production)	5700	5700	V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety-Related Certifications

VDE	CSA	UL	CQC	TUV
Plan to certify according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01	Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1	Plan to certify according to UL 1577 Component Recognition Program	Plan to certify according to GB 4943.1-2011	Plan to certify according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013
Reinforced insulation Maximum transient isolation voltage, 8000 V_PK; Maximum repetitive peak isolation voltage, 2121 V_PK (DW), 2828 V_PK (DWW); Maximum surge isolation voltage, 8000 V_PK	Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 V_RMS (DW package) and 1450 V_RMS (DWW package) max working voltage (pollution degree 2, material group I);	Single protection, 5700 V_RMS	Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 V_RMS maximum working voltage	5700 V_RMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 V_RMS (DW package) and 1000 V_RMS (DWW package)
	2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 V_RMS (354 V_PK) max working voltage (DW package)	Single protection, 5700 V_RMS		5700 V_RMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 V_RMS (DW package) and 1450 V_RMS (DWW package)
Certification planned	Certification planned	Certification planned	Certification planned	Certification planned

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
DW PACKAGE
I_S	Safety input, output, or supply current	R_θJA = 82°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 3	277	mA
		R_θJA = 82°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 3	423
		R_θJA = 82°C/W, V_I = 2.75 V, T_J = 150°C, T_A = 25°C, see Figure 3	554
P_S	Safety input, output, or total power	R_θJA = 82°C/W, T_J = 150°C, T_A = 25°C, see Figure 5	1524	mW
T_S	Maximum safety temperature		150	°C
DWW PACKAGE
I_S	Safety input, output, or supply current	R_θJA = 84.6°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 4	269	mA
		R_θJA = 84.6°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 4	410
		R_θJA = 84.6°C/W, V_I = 2.75 V, T_J = 150°C, T_A = 25°C, see Figure 4	537
P_S	Safety input, output, or total power	R_θJA = 84.6°C/W, T_J = 150°C, T_A = 25°C, see Figure 6	1478	mW
T_S	Maximum safety temperature		150	°C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 DC Electrical Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_IN(EN)	Leakage Current on ENx pins	Internal pullup on ENx pins		13	40	μA
V_CC+(UVLO)	Positive-going undervoltage-lockout (UVLO) threshold				2.25	V
V_CC–(UVLO)	Negative-going UVLO threshold		1.7			V
V_HYS(UVLO)	UVLO threshold hysteresis			0.2		V
V_EN(ON)	EN pin turn-on threshold				0.7 V_CCx	V
V_EN(OFF)	EN pin turn-off threshold		0.3 V_CCx			V
V_EN(HYS)	EN pin threshold hysteresis			0.1 V_CCx		V
CMTI	Common-mode transient immunity	V_I = V_CCI⁽¹⁾ or 0 V; V_CM = 1000 V; see Figure 25	100	120		kV/μs
LVDS TX
\|V_OD\|	TX DC output differential voltage	R_L = 100 Ω, See Figure 26	250	350	450	mV
∆V_OD	Change in TX DC output differential between logic 1 and 0 states	R_L = 100 Ω, see Figure 26	–10	0	10	mV
V_OC	TX DC output common mode voltage	R_L = 100 Ω, see Figure 26	1.125	1.2	1.375	V
∆V_OC	TX DC common mode voltage difference	R_L = 100 Ω, see Figure 26	–25	0	25	mV
I_OS	TX output short circuit current through OUTx	OUTx = 0			10	mA
I_OS	TX output short circuit current through OUTx	OUTxP = OUTxM			10	mA
I_OZ	TX output current when in high impedance	ENx = 0, OUTx from 0 to V_CC	–5		5	µA
C_OUT	TX output pad capacitance on OUTx at 1 MHz	DW package: ENx = 0, DC offset = V_CC / 2, Swing = 200 mV, f = 1 MHz		10		pF
C_OUT	TX output pad capacitance on OUTx at 1 MHz	DWW package: ENx = 0, DC offset = V_CC / 2, Swing = 200 mV, f = 1 MHz		10		pF
LVDS RX
V_IC	RX input common mode voltage	V_CC1, V_CC2 ≥ 3 V	0.5 \|V_ID\|	1.2	2.4 – 0.5 \|V_ID\|	V
V_IC	RX input common mode voltage	V_CC1, V_CC2 < 3 V	0.5 \|V_ID\|	1.2	V_CCx – 0.6 – 0.5 \|V_ID\|	V
V_IT1	Positive going RX input differential threshold	Across V_IC			50	mV
V_IT2	Negative going RX input differential threshold	Across V_IC	–50			mV
I_INx	Input current on INx	From 0 to V_CCx (each input independently)		10	20	µA
I_INxP – I_INxM	Input current balance	From 0 to V_CCx	–6		6	µA
C_IN	RX input pad capacitance on INx at 1 MHz	DW package: DC offset = 1.2 V, Swing = 200 mV, f = 1 MHz		6.6		pF
C_IN	RX input pad capacitance on INx at 1 MHz	DWW package: DC offset = 1.2 V, Swing = 200 mV, f = 1 MHz		7.5		pF

(1) V_CCI = Input-side V_CCx; V_CCO = Output-side V_CCx.

6.10 DC Supply Current Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
ISO7821LL
I_CC1 I_CC2	Supply current side 1 and side 2	2.25 V < V_CC1, V_CC2 < 3.6 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.2	3.3	mA
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	3.4	5.1
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	6.1	9.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	7.4	11.1
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	6.7	10.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	7.4	11.5
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	8.3	12.5
		4.5 V < V_CC1, V_CC2 < 5.5 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.2	3.4
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	3.5	5.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	6.4	9.8
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	7.8	11.7
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	7.1	10.8
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	8.1	12.1
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	9.5	14.1
ISO7820LL
I_CC1	Supply current side 1	2.25 V < V_CC1, V_CC2 < 3.6 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.7	4.3	mA
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	5.3	7.9
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID≥ 50 mV	2.7	4.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	5.2	8
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	4	6.1
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	4.1	6.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	4.3	6.4
		4.5 V < V_CC1, V_CC2 < 5.5 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.8	4.4
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	5.5	8.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	2.9	4.5
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	5.5	8.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	4.2	6.3
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	4.3	6.4
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	4.5	6.6
ISO7820LL (continued)
I_CC2	Supply current side 2	2.25 V < V_CC1, V_CC2 < 3.6 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	1.1	1.7	mA
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	1.1	1.7
			V_ID≥ 50 mV	9.1	13.7
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	9.2	13.9
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	9.2	13.8
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	10.3	15.5
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	12.1	17.9
		4.5 V < V_CC1, V_CC2 < 5.5 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	1.2	1.8
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	1.2	1.8
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	9.7	14.7
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	9.7	14.8
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 1 Mbps	9.7	14.7
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	11.5	17.3
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 100 Mbps	14.2	21

6.11 Switching Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LVDS CHANNEL
t_PLH t_PHL	Propagation delay time			17	25	ns
PWD	Pulse width distortion \|t_PHL – t_PLH\|			0	4.5	ns
t_sk(o)	Channel-to-channel output skew time	Same directional channels, same voltage and temperature			2.5	ns
t_sk(pp)	Part-part skew	Same directional channels, same voltage and temperature			4.5	ns
t_CMset	Common-mode settling time after EN = 0 to EN = 1 transition.	Common-mode capacitive load = 100 pF to 0.5 nF			20	µs
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V, see Figure 24		0.2	9	µs
t_ie	Time interval error, or peak-to-peak jitter	2¹⁶ – 1 PRBS data at 100 Mbps; RX V_ID = 350 mV_PP, 1 ns t_rf 10% to 90%, T_A = 25°C, V_CC1, V_CC2 = 3.3 V		1		ns
LVDS TX AND RX
t_rf	TX differential rise/fall times (20% to 80%)	See Figure 22	300	780	1380	ps
∆V_OC(pp)	TX common-mode voltage peak-to-peak at 100 Mbps			0	150	mV_PP
t_PLZ, t_PHZ	TX disable time—valid output to HiZ	See Figure 23		10	20	ns
t_PZH	Enable propagation delay, high impedance-to-high output	See Figure 23		10	20	ns
t_PZL	Enable propagation delay, high impedance-to-low output	See Figure 23		2	2.5	μs
\|V_ID\|	Magnitude of RX input differential voltage for valid operation	Driven with voltage sources on RX pins, see the figures in the Parameter Measurement Information section	100		600	mV
t_rf(RX)	Allowed RX input differential rise and fall times (20% to 80%)	See Figure 27		1	0.3 × UI⁽¹⁾	ns

(1) UI is the unit interval.

6.12 Insulation Characteristics Curves

ISO7820LL ISO7821LL tddb_curve_reinforced_dw.gif

T_A upto 150°C	Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 V_RMS

Figure 1. Reinforced Isolation Capacitor Lifetime Projection for Devices in DW Package

Figure 3. Thermal Derating Curve for Limiting Current for DW Package

Figure 5. Thermal Derating Curve for Limiting Power for DW Package

ISO7820LL ISO7821LL tddb_curve_reinforced_dww.gif

T_A upto 150°C	Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 V_RMS

Figure 2. Reinforced Isolation Capacitor Lifetime Projection for Devices in DWW Package

Figure 4. Thermal Derating Curve for Limiting Current for DWW Package

Figure 6. Thermal Derating Curve for Limiting Power for DWW Package

6.13 Typical Characteristics

T_A = 25°C

CH-A toggle

Figure 7. ISO7821LL Supply Current vs Data Rate (CH-A)

T_A = 25°C

Figure 9. ISO7821LL Supply Current vs V_CCx Output Supply Voltage

Data rate = 100 Mbps

CH-B toggle

Figure 11. ISO7821LL Supply Current vs Temperature
(CH-B)

T_A = 25°C

CH-B toggle

Figure 13. ISO7820LL Supply Current vs Data Rate
(CH-B)

Data rate = 100 Mbps

CH-A toggle

Figure 15. ISO7820LL Supply Current vs Temperature
(CH-A)

Figure 17. Propagation Delay Time vs Temperature

T_A = 25°C

Figure 19. Output Voltage vs V_CCx Output Supply Voltage

ISO7820LL ISO7821LL waveform_disable_time_sllset8.gif

Figure 21. Disable Time (t_PLZ, t_PHZ)

T_A = 25°C

CH-B toggle

Figure 8. ISO7821LL Supply Current vs Data Rate (CH-B)

Data rate = 100 Mbps

CH-A toggle

Figure 10. ISO7821LL Supply Current vs Temperature
(CH-A)

T_A = 25°C

CH-A toggle

Figure 12. ISO7820LL Supply Current vs Data Rate
(CH-A)

T_A = 25°C

Figure 14. ISO7820LL Supply Current vs V_CCx Output Supply Voltage

Data rate = 100 Mbps

CH-B toggle

Figure 16. ISO7820LL Supply Current vs Temperature
(CH-B)

T_A = 25°C

Figure 18. Propagation Delay Time vs V_CCx Output Supply Voltage

ISO7820LL ISO7821LL waveform_disable_to_enable_time_sllset8.gif

Figure 20. Disable to Enable Time (t_PZH, t_PZL)

7 Parameter Measurement Information

ISO7820LL ISO7821LL switch_test_circuit_sllset5.gif

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t_r ≤ 3 ns, t_f ≤ 3 ns, Z_O = 50 Ω.

B. C_P = 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 22. Switching Characteristics Test Circuit and Voltage Waveforms

ISO7820LL ISO7821LL delay_time_sllset8.gif

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
t_r ≤ 3 ns, t_f ≤ 3 ns, Z_O = 50 Ω.

B. C_L = 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 23. Enable and Disable Propagation Delay Time Test Circuit and Waveform

ISO7820LL ISO7821LL failsafe_sllset5.gif

A. C_L = 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 24. Default Output Delay Time Test Circuit and Voltage Waveforms

ISO7820LL ISO7821LL com_tran_imm_test_circ_sllset5.gif

A. C_L = 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 25. Common-Mode Transient Immunity Test Circuit

ISO7820LL ISO7821LL driver_test_circuit_sllset8.gif

Figure 26. Driver Test Circuit

ISO7820LL ISO7821LL td_definitions_sllset8.gif

Figure 27. Voltage Definitions and Waveforms

8 Detailed Description

8.1 Overview

The ISO782xLL is a family of isolated LVDS buffers. The differential signal received on the LVDS input pins is first converted to CMOS logic levels. The signal is then transmitted across a silicon-dioxide (SiO₂) based capacitive-isolation barrier using an on-off keying (OOK) modulation scheme. A high frequency carrier transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS outputs by a differential driver. These devices incorporate advanced circuit techniques to maximize CMTI performance and minimize radiated emissions.

The ISO782xLL family of devices is TIA/EIA-644-A standard compliant. The LVDS transmitters drive a minimum differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receivers are capable of detecting differential signals ≥50 mV in magnitude. The device consumes 10 mA per channel at 100 Mbps with 5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO782xLL family of devices.

8.2 Functional Block Diagram

8.3 Feature Description

The ISO782xLL family of devices is available in two channel configurations with a default differential high-output state.

PART NUMBER	CHANNEL DIRECTION	RATED ISOLATION	MAXIMUM DATA RATE	DEFAULT DIFFERENTIAL OUTPUT
ISO7820LL	2 Forward	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High
ISO7821LL	1 Forward, 1 Reverse	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High

(1) See the Safety-Related Certifications section for detailed isolation ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes for the ISO782xLL family of devices.

Table 1. ISO782xLL Function Table⁽¹⁾

V_CCI	V_CCO	INPUT (INx±)⁽²⁾	OUTPUT ENABLE (ENx)	OUTPUT (OUTx±)⁽³⁾	COMMENTS
PU	PU	H	H or open	H	Normal Operation: A channel output assumes the logic state of the input.
		L	H or open	L
		I	H or open	H or L
X	PU	X	L	Z	A low-logic state at the output enable causes the outputs to be in high impedance.
PD	PU	X	H or open	H	Default mode: When V_CCI is unpowered, a channel output assumes the logic high state. When V_CCI transitions from unpowered to powered up, a channel output assumes the logic state of the input. When V_CCI transitions from powered up to unpowered, a channel output assumes the selected default high state.
X	PD	X	X	Undetermined	When V_CCO is unpowered, a channel output is undetermined. When V_CCO transitions from unpowered to powered-up, a channel output assumes the logic state of the input

(1) V_CCI = input-side V_CC; V_CCO = output-side V_CC; PU = powered up (V_CCx ≥ 2.25 V); PD = powered down (V_CCx ≤ 1.7 V); X = irrelevant

(2) Input (INx±): H = high level (V_ID ≥ 50 mV); L = low level (V_ID ≤ –50 mV); I = indeterminate (–50 mV < V_ID < 50 mV)

(3) Output (OUTx±): H = high level (V_OD ≥ 250 mV); L = low level (V_OD ≤ –250 mV); Z = high impedance.

8.4.1 Device I/O Schematics

ISO7820LL ISO7821LL device_IO_sllset8.gif

Figure 28. Device I/O Schematics