ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | IRQ_EN | ||||||
R | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | Reserved | R | Reserved | |
0 | IRQ_EN | R/W | 0 | When enabled by this field, the IRQ output is driven high to communicate IRQ events.
0 – IRQ output is high-impedance (default) 1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition |