LP5912-Q1 汽车类 500mA 低噪声、低 IQ LDO
- ZHCSFP8C December 2015 – September 2016 LP5912-Q1
  
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LP5912-Q1 汽车类 500mA 低噪声、低 IQ LDO

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

适用于汽车电子应用
具有符合 AEC Q100 的下列结果：
- 器件温度 1 级：-40℃ 至 +125℃ 的环境运行温度范围
- 器件人体放电模式 (HBM) 分类等级 2
- 器件组件充电模式 (CDM) 分类等级 C6
输入电压范围：1.6V 至 6.5V
输出电压范围：0.8V 至 5.5V
输出电流最高达 500 mA
低输出电压噪声：12µV_RMS 典型值
1kHz 时的电源抑制比 (PSRR)：75dB（典型值）
输出电压容差 (V_OUT ≥ 3.3V)：±2%
低 I_Q（使能时，无负载）：30µA（典型值）
低压降 (V_OUT ≥ 3.3V)：500mA 负载时典型值为 95mV
与 1µF 陶瓷输入和输出电容搭配使用，性能稳定
热过载保护和短路保护
反向电流保护
无需噪声旁路电容
自动输出放电实现快速关断
电源正常状态输出具有 140µs 典型延迟
内部软启动限制浪涌电流
–40°C 至 +125°C 的运行结温范围

2 应用

车用信息娱乐
车载通讯系统
高级驾驶员辅助系统 (ADAS) 摄像机和雷达
导航系统

3 说明

LP5912-Q1 是一款能提供高达 500mA 输出电流的低噪声 LDO。LP5912-Q1 器件专为满足射频 (RF) 和模拟电路的要求而设计，具备低噪声、高 PSRR、低静态电流以及低线路或负载瞬态响应等特性。LP5912-Q1 无需噪声旁路电容便可提供出色的噪声性能，并且支持远距离安置输出电容。

此器件适合与 1µF 输入和 1µF 输出陶瓷电容搭配使用（无需独立的噪声旁路电容）。

其固定输出电压介于 0.8V 和 5.5V 之间（以 25mV 为单位增量）。如需特定的电压选项，请联系德州仪器 (TI) 销售代表。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LP5912-Q1	WSON (6)	2.00mm x 2.00mm

要了解所有可用封装，请参见数据表末尾的封装选项附录 (POA)。

空白

简化电路原理图

4 修订历史记录

Changes from B Revision (June 2016) to C Revision

Changed 数据表标题和 列表的措辞应用Go
Changed 的第一句的措辞说明Go

Changes from A Revision (April 2016) to B Revision

Changed 第 1 页的“线性稳压器”改为“LDO”Go

Changes from * Revision (December 2015) to A Revision

Changed 器件状态从“预览”改为“量产数据”Go
Changed Block DiagramGo

5 Voltage Options

This device is capable of providing fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. For all available package and voltage options, see the POA at the end of this datasheet. Contact Texas Instruments Sales for specific voltage option needs.

6 Pin Configuration and Functions

DRV Package

6-Pin WSON With Thermal Pad

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NUMBER	NAME	I/O	DESCRIPTION
1	OUT	O	Regulated output voltage
2	NC	—	No internal connection. Leave open, or connect to ground.
3	PG	O	Power-good indicator. Requires external pullup.
4	EN	I	Enable input. Logic high = device is ON, logic low = device is OFF, with internal 3-MΩ pulldown.
5	GND	G	Ground
6	IN	I	Unregulated input voltage
—	Exposed thermal pad	—	Connect to copper area under the package to improve thermal performance. The use of thermal vias to transfer heat to inner layers of the PCB is recommended. Connect the thermal pad to ground, or leave floating. Do not connect the thermal pad to any potential other than ground.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_IN	Input voltage	–0.3	7	V
V_OUT	Output voltage	–0.3	7	V
V_EN	Enable input voltage	–0.3	7	V
V_PG	Power Good (PG) pin OFF voltage	–0.3	7	V
T_J	Junction temperature		150	°C
P_D	Continuous power dissipation⁽³⁾	Internally Limited		W
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) Internal thermal shutdown circuitry protects the device from permanent damage.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_IN	Input supply voltage	1.6	6.5	V
V_OUT	Output voltage	0.8	5.5	V
V_EN	Enable input voltage	0	V_IN	V
V_PG	PG pin OFF voltage	0	6.5	V
I_OUT	Output current	0	500	mA
T_J-MAX-OP	Operating junction temperature⁽²⁾	–40	125	°C

(1) All voltages are with respect to the GND pin.

(2) T_J-MAX-OP = (T_A(MAX) + (P_D(MAX) × R_θJA )).

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP5912-Q1	UNIT
		DRV (WSON)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance, High-K⁽²⁾	71.2⁽³⁾	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	93.7	°C/W
R_θJB	Junction-to-board thermal resistance	40.7	°C/W
ψ_JT	Junction-to-top characterization parameter	2.5	°C/W
ψ_JB	Junction-to-board characterization parameter	41.1	°C/W
ψ_JC(bot)	Junction-to-case (bottom) thermal resistance	11.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(3) The PCB for the WSON (DRV) package R_θJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

7.5 Electrical Characteristics

V_IN = V_OUT(NOM) + 0.5 V or 1.6 V, whichever is greater; V_EN = 1.3 V, C_IN = 1 µF, C_OUT = 1 µF, I_OUT = 1 mA (unless otherwise stated).⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OUTPUT VOLTAGE
ΔV_OUT	Output voltage tolerance	For V_OUT(NOM) ≥ 3.3 V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–2%		2%
		For 1.1 V ≤ V_OUT(NOM) < 3.3 V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–3%		3%
		For V_OUT(NOM) < 1.1 V: 1.6 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–3%		3%
	Line regulation	For V_OUT(NOM) ≥ 1.1 V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V		0.8		%/V
	Line regulation	For V_OUT(NOM) < 1.1 V: 1.6 V ≤ V_IN ≤ 6.5 V		0.8		%/V
	Load regulation	I_OUT = 1 mA to 500 mA		0.0022		%/mA
CURRENT LEVELS
I_SC	Short-circuit current limit	T_J = 25°C, see⁽⁴⁾	700	900	1100	mA
I_RO	Reverse leakage current⁽⁵⁾	V_IN < V_OUT		10	150	µA
I_Q	Quiescent current⁽⁶⁾	V_EN = 1.3 V, I_OUT = 0 mA		30	55	µA
I_Q	Quiescent current⁽⁶⁾	V_EN = 1.3 V, I_OUT = 500 mA		400	600	µA
I_Q(SD)	Quiescent current, shutdown mode⁽⁶⁾	V_EN = 0 V –40°C ≤ T_J ≤ 85°C		0.2	1.5	µA
I_Q(SD)	Quiescent current, shutdown mode⁽⁶⁾	V_EN = 0 V		0.2	5	µA
I_G	Ground current⁽⁷⁾	V_EN = 1.3 V, I_OUT = 0 mA		35		µA
V_DO DROPOUT VOLTAGE
V_DO	Dropout voltage⁽⁸⁾	I_OUT = 500 mA, 1.6 V ≤ V_OUT(NOM) < 3.3 V		170	250	mV
V_DO	Dropout voltage⁽⁸⁾	I_OUT = 500 mA, 3.3 V ≤ V_OUT(NOM) ≤ 5.5 V		95	180	mV
V_IN to V_OUT RIPPLE REJECTION
PSRR	Power Supply Rejection Ratio⁽¹⁰⁾	ƒ = 100 Hz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		80		dB
		ƒ = 1 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		75
		ƒ = 10 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		65
		ƒ = 100 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		40
		ƒ = 100 Hz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 1 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 10 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 100 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		40
OUTPUT NOISE VOLTAGE
e_N	Noise voltage	I_OUT = 1 mA, BW = 10 Hz to 100 kHz		12		µV_RMS
e_N	Noise voltage	I_OUT = 500 mA, BW = 10 Hz to 100 kHz		12		µV_RMS
THERMAL SHUTDOWN
T_SD	Thermal shutdown temperature			160		°C
T_HYS	Thermal shutdown hysteresis			15		°C
LOGIC INPUT THRESHOLDS
V_EN(OFF)	OFF threshold	V_IN = 1.6 V to 6.5 V V_EN falling until device is disabled			0.3	V
V_EN(ON)	ON threshold	1.6 V ≤ V_IN≤ 6.5 V V_EN rising until device is enabled	1.3			V
I_EN	Input current at EN pin⁽⁹⁾	V_EN = 6.5 V, V_IN = 6.5 V		2.5		µA
I_EN	Input current at EN pin⁽⁹⁾	V_EN = 0 V, V_IN = 3.3 V		0.001		µA
PG_HTH	PG high threshold (% of nominal V_OUT)			94%
PG_LTH	PG low threshold (% of nominal V_OUT)			90%
V_OL(PG)	PG pin low-level output voltage	V_OUT < PG_LTH, sink current = 1 mA			100	mV
I_lKG(PG)	PG pin leakage current	V_OUT < PG_HTH, V_PG = 6.5 V			1	µA
t_PGD	PG delay time	Time from V_OUT > PG threshold to PG toggling		140		µs
TRANSITION CHARACTERISTICS
ΔV_OUT	Line transients⁽¹⁰⁾	For V_IN ↑ and V_OUT(NOM) ≥ 1.1 V: V_IN = (V_OUT(NOM) + 0.5 V) to (V_OUT(NOM) + 1.1 V), V_IN t_rise = 30 µs			1	mV
		For V_IN ↑ and V_OUT(NOM) < 1.1 V: V_IN = 1.6 V to 2.2 V, V_IN t_rise = 30 µs			1
		For V_IN ↓ and V_OUT(NOM) ≥ 1.1 V: V_IN = (V_OUT(NOM) + 1.1 V) to (V_OUT(NOM) + 0.5 V) V_IN t_fall = 30 µs	–1
		For V_IN ↓ and V_OUT(NOM) < 1.1 V: V_IN = 2.2 V to 1.6 V V_IN t_fall = 30 µs	–1
	Load transients⁽¹⁰⁾	I_OUT = 5 mA to 500 mA I_OUT t_rise = 10 µs	–45			mV
	Load transients⁽¹⁰⁾	I_OUT = 500 mA to 5 mA I_OUT t_fall = 10 µs			45	mV
	Overshoot on start-up⁽¹⁰⁾	Stated as a percentage of V_OUT(NOM)			5%
t_ON	Turnon time	From V_EN > V_EN(ON) to V_OUT = 95% of V_OUT(NOM)		200		µs
OUTPUT AUTO DISCHARGE RATE
R_AD	Output discharge pulldown resistance	V_EN = 0 V, V_IN = 3.6 V		100		Ω

(1) All voltages are with respect to the device GND pin, unless otherwise stated.

(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_A = 25°C, and are provided for reference purposes only.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (R_θJA), as given by the following equation: T_A-MAX = T_J-MAX-OP – (R_θJA × P_D-MAX).

(4) Short-circuit current (I_SC) is equivalent to current limit. To minimize thermal effects during testing, I_SC is measured with V_OUT pulled to 100 mV below its nominal voltage.

(5) Reverse current (IRO) is measured at the IN pin.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT.

(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device (I_Q + I_EN).

(8) Dropout voltage (V_DO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its nominal value when V_IN = V_OUT + 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with the minimum operating voltage requirement cannot be assured.

(9) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.

(10) This specification is ensured by design.

7.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP	MAX	UNIT
C_IN	Input capacitance⁽²⁾	Capacitance for stability	0.7	1		µF
C_OUT	Output capacitance⁽²⁾	Capacitance for stability	0.7	1	10	µF
ESR	Output voltage⁽²⁾		5		500	mΩ

(1) The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V, and Z5U may be used with consideration of the application conditions.

(2) This specification is verified by design.

7.7 Typical Characteristics

Unless otherwise stated: V_IN = V_OUT + 0.5 V, V_EN = V_IN, I_OUT = 1 mA, C_IN = 1 µF, C_OUT = 1 µF, T_J = 25°C, unless otherwise stated.

Figure 1. V_EN Thresholds vs Input Voltage

Figure 3. LP5912-1.8 Output Voltage, V_PG vs Input Voltage

V_IN = 0 V to 1.6 V		I_OUT = 1 mA

Figure 5. LP5912-0.9 Power Up

V_IN = 0 V to 2.3 V		I_OUT = 1 mA

Figure 7. LP5912-1.8 Power Up

V_IN = 0 V to 3.8 V		I_OUT = 1 mA

Figure 9. LP5912-3.3 Power Up

I_OUT = 0 mA

Figure 11. LP5912-0.9 I_Q (No Load) vs V_IN

I_OUT = 0 mA

Figure 13. LP5912-3.3 I_Q (No Load) vs V_IN

V_EN = 0 V

Figure 15. LP5912-1.8 I_Q_(SD) vs V_IN

V_IN = 1.6 V

Figure 17. LP5912-0.9 I_GND vs I_OUT

Figure 19. LP5912-3.3 I_GND vs I_OUT

V_IN = 1.6 V

Figure 21. LP5912-0.9 PSRR vs Frequency

Figure 23. LP5912-1.8 PSRR vs Frequency

Figure 25. LP5912-3.3 PSRR vs Frequency

V_IN = 2.2 V to 1.6 V		t_fall = 30 µs

Figure 27. LP5912-0.9 Line Transient

V_IN = 2.9 V to 2.3 V		t_fall = 30 µs

Figure 29. LP5912-1.8 Line Transient

V_IN = 4.4 V to 3.8 V		t_fall = 30 µs

Figure 31. LP5912-3.3 Line Transient

V_IN = 1.6 V	I_OUT = 500 mA to 5 mA	t_fall = 10 µs

Figure 33. LP5912-0.9 Load Transient Response

I_OUT = 500 mA to 5 mA		t_fall = 10 µs

Figure 35. LP5912-1.8 Load Transient Response

I_OUT = 500 mA to 5 mA		t_fall = 10 µs

Figure 37. LP5912-3.3 Load Transient Response

I_OUT = 0 mA

C_OUT = 1 µF

Figure 39. LP5912-1.8 V_OUT vs V_EN(OFF)

I_OUT = 1 mA

C_OUT = 1 µF

Figure 41. LP5912-1.8 V_OUT vs V_EN(OFF)

I_OUT = 500 mA

C_OUT = 1 µF

Figure 43. LP5912-1.8 V_OUT vs V_EN(OFF)

Figure 45. LP5912-3.3 Dropout Voltage (V_DO) vs I_OUT

Figure 47. LP5912-1.8 Noise vs Frequency

I_OUT = 0 mA (No Load)

Figure 49. LP5912-3.3 Turnon Time vs Junction Temperature

C_IN = Open	I_OUT = 1 mA	C_OUT = 1 µF

Figure 51. LP5912-3.3 In-Rush Current

	C_IN = Open	I_OUT = 1 mA	C_OUT = 10 µF

Figure 53. LP5912-3.3 In-Rush Current

Figure 2. LP5912-0.9 Output Voltage, V_PG vs Input Voltage

Figure 4. LP5912-3.3 Output Voltage, V_PG vs Input Voltage

V_IN = 0 V to 1.6 V		I_OUT = 500 mA

Figure 6. LP5912-0.9 Power Up

V_IN = 0 V to 2.3 V		I_OUT = 500 mA

Figure 8. LP5912-1.8 Power Up

V_IN = 0 V to 3.8 V		I_OUT = 500 mA

Figure 10. LP5912-3.3 Power Up

I_OUT = 0 mA

Figure 12. LP5912-1.8 I_Q (No Load) vs V_IN

V_EN = 0 V

Figure 14. LP5912-0.9 I_Q_(SD) vs V_IN

V_EN = 0 V

Figure 16. LP5912-3.3 I_Q_(SD) vs V_IN

Figure 18. LP5912-1.8 I_GND vs I_OUT

V_IN = 1.6 V		I_OUT = 20 mA

Figure 20. LP5912-0.9 PSRR vs Frequency

I_OUT = 20 mA

Figure 22. LP5912-1.8 PSRR vs Frequency

I_OUT = 20 mA

Figure 24. LP5912-3.3 PSRR vs Frequency

V_IN = 1.6 V to 2.2 V		t_rise = 30 µs

Figure 26. LP5912-0.9 Line Transient

V_IN = 2.3 V to 2.9 V		t_rise = 30 µs

Figure 28. LP5912-1.8 Line Transient

V_IN = 3.8 V to 4.4 V		t_rise = 30 µs

Figure 30. LP5912-3.3 Line Transient

V_IN = 1.6 V	I_OUT = 5 mA to 500 mA	t_rise = 10 µs

Figure 32. LP5912-0.9 Load Transient Response

I_OUT = 5 mA to 500 mA		t_rise = 10 µs

Figure 34. LP5912-1.8 Load Transient Response

I_OUT = 5 mA to 500 mA		t_rise = 10 µs

Figure 36. LP5912-3.3 Load Transient Response

I_OUT = 0 mA		C_OUT = 1 µF

Figure 38. LP5912-1.8 V_OUT vs V_EN(ON)

I_OUT = 1 mA

C_OUT = 1 µF

Figure 40. LP5912-1.8 V_OUT vs V_EN(ON)

I_OUT = 500 mA

C_OUT = 1 µF

Figure 42. LP5912-1.8 V_OUT vs V_EN(ON)

Figure 44. LP5912-1.8 Dropout Voltage (V_DO) vs I_OUT

V_IN = 1.6 V

Figure 46. LP5912-0.9 Noise vs Frequency

Figure 48. LP5912-3.3 Noise vs Frequency

C_IN = Open	I_OUT = 500 mA	C_OUT = 1 µF

Figure 50. LP5912-3.3 In-Rush Current

C_IN = Open	I_OUT = 500 mA	C_OUT = 10 µF

Figure 52. LP5912-3.3 In-Rush Current

8 Detailed Description

8.1 Overview

The LP5912-Q1 is a low-noise, high PSRR, LDO capable of sourcing a 500-mA load. The LP5912-Q1 can operate down to 1.6-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive communication components to battery-powered system.

The LP5912-Q1 Functional Block Diagram contains several features, including:

Internal output resistor divider feedback;
Small size and low-noise internal protection circuit current limit;
Reverse current protection;
Current limit and in-rush current protection;
Thermal shutdown;
Output auto discharge for fast turnoff; and
Power-good output, with fixed 140-µs typical delay.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Enable (EN)

The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the V_EN(ON) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the V_EN(OFF) threshold to ensure that the device is fully disabled and the automatic output discharge is activated.

When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic discharge is ON.

8.3.2 Output Automatic Discharge (R_AD)

The LP5912-Q1 output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the EN pin is low. Note that if the LP5912-Q1 EN pin is low (the device is OFF) and the OUT pin is held high by a secondary supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground.

8.3.3 Reverse Current Protection (I_RO)

The LP5912-Q1 input is protected against reverse current when output voltage is higher than the input. In the event that extra output capacitance is used at the output, a power-down transient at the input would normally cause a large reverse current through a conventional regulator. The LP5912-Q1 includes a reverse voltage detector that trips when V_IN drops below V_OUT, shutting off the regulator and opening the PMOS body diode connection, preventing any reverse current from the OUT pin from flowing to the IN pin.

If the LP5912 EN pin is low (the LP5912 is OFF) and the OUT pin is held high by a secondary supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground. This is not reverse current, this is automatic discharge pulldown current.

Note that reverse current (I_RO) is measured at the IN pin.

8.3.4 Internal Current Limit (I_SC)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate continuously at the I_SC current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

8.3.5 Thermal Overload Protection (T_SD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which allows the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

8.3.6 Power-Good Output (PG)

The LP5912-Q1 device has a power-good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (PG_LTH), the PG pin open-drain output engages (low impedance to GND). When the output voltage rises above the PG threshold voltage (PGV_HTH), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.

The input supply, V_IN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin output status is valid. The PG pin output status is undefined when V_IN is less than 1.6 V.

In power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output voltage rises above the PG_HTH threshold voltage. If the output voltage rises above the PG_HTH threshold and then falls below the PG_LTH threshold voltage the PG pin falls immediately with no delay time.

If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to ground or left floating.

8.4 Device Functional Modes

8.4.1 Enable (EN)

The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the V_EN(ON) threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin voltage is lower than the V_EN(OFF) threshold, the output stage is disabled, the PG pin goes low, and the output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the internal 100-Ω (typical) output auto discharge pulldown resistance.

8.4.2 Minimum Operating Input Voltage (V_IN)

The LP5912-Q1 device does not include any dedicated UVLO circuit. The device internal circuit is not fully functional until V_IN is at least 1.6 V. The output voltage is not regulated until V_IN has reached at least the greater of 1.6 V or (V_OUT + V_DO).

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP5912-Q1 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR, low quiescent current, and low line or load transient response. The device offers excellent noise performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a value of 1 μF. The device delivers this performance in an industry standard WSON package, which for this device is specified with an operating junction temperature (T_J) of –40°C to +125°C.

9.2 Typical Application

Figure 54 shows the typical application circuit for the LP5912-Q1. Input and output capacitances may need to be increased above the 1-μF minimum for some applications.

Figure 54. LP5912-Q1 Typical Application

9.2.1 Design Requirements

For typical RF linear regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
Input voltage	1.6 to 6.5 V
Output voltage	0.8 to 5.5 V
Output current	500 mA
Output capacitor	1 to 10 µF
Input/output capacitor ESR range	5 mΩ to 500 mΩ

9.2.2 Detailed Design Procedure

9.2.2.1 External Capacitors

Like most low-dropout regulators, the LP5912-Q1 requires external capacitors for regulator stability. The device is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance.

9.2.2.2 Input Capacitor

An input capacitor is required for stability. The input capacitor must be at least equal to, or greater than, the output capacitor for good load-transient performance. A capacitor of at least 1 µF must be connected between the LP5912-Q1 IN pin and ground for stable operation over full load-current range. It is acceptable to have more output capacitance than input, as long as the input is at least 1 µF.

The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

To ensure stable operation it is essential that good PCB practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to connect the battery or other power source to the LP5912-Q1, increasing the value of the input capacitor to at least 10 µF is recommended. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (such as a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains 1 μF ±30% over the entire operating temperature range.

9.2.2.3 Output Capacitor

The LP5912-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with an ESR from 5 mΩ to 500 mΩ, is suitable in the LP5912-Q1 application circuit. For this device the output capacitor must be connected between the OUT pin with a good connection back to the GND pin.

Tantalum or film capacitors may also be used at the device output, V_OUT, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value that is within the range 5 mΩ to 500 mΩ for stability.

9.2.2.4 Capacitor Characteristics

The LP5912-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest, least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP5912-Q1.

The preferred choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. While it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

9.2.2.5 Remote Capacitor Operation

To ensure stability the LP5912-Q1 requires at least a 1-μF capacitor at the OUT pin. There is no strict requirement about the location of the output capacitor in regards to the LDO OUT pin; the output capacitor may be located 5 to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to the OUT pin if there are already respective capacitors in the system. This placement flexibility requires that the output capacitor be connected directly between the LP5912-Q1 OUT pin and GND pin with no vias. This remote capacitor feature can help users to minimize the number of capacitors in the system.

As a good design practice, keep the wiring parasitic inductance at a minimum, which means using as wide as possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground layer as possible, avoiding vias on the path. If there is a need to use vias, implement as many as possible vias between the connection layers. Keeping parasitic wiring inductance less than 35 nH is recommended. For applications with fast load transients use an input capacitor equal to, or larger than, the sum of the capacitance at the output node for the best load-transient performance.

9.2.2.6 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1.

Equation 1. P_D(MAX) = (V_IN(MAX) – V_OUT) × I_OUT

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that is greater than the dropout voltage (V_DO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance.

On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper PCB area.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to Equation 2 or Equation 3:

Equation 2. T_J(MAX) = T_A(MAX) + (R_θJA × P_D(MAX))

Equation 3. P_D = (T_J(MAX) – T_A(MAX)) / R_θJA

Unfortunately, this R_θJAis highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, R_θJA is actually the sum of the package junction-to-case (bottom) thermal resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

9.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (Ψ_JT and Ψ_JB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5.

Equation 4. T_J(MAX) = T_TOP + (Ψ_JT × P_D(MAX))

where

P_D(MAX) is explained in Equation 3
T_TOP is the temperature measured at the center-top of the device package.

Equation 5. T_J(MAX) = T_BOARD + (Ψ_JB × P_D(MAX))

where

P_D(MAX) is explained in Equation 3.
T_BOARDis the PCB surface temperature measured 1 mm from the device package and centered on the package edge.

For more information about the thermal characteristics Ψ_JT and Ψ_JB, see Semiconductor and IC Package Thermal Metrics ; for more information about measuring T_TOP and T_BOARD, see Using New Thermal Metrics ; and for more information about the EIA/JEDEC JESD51 PCB used for validating R_θJA, see the TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available at www.ti.com.

9.2.3 Application Curves

V_IN = 2.3 V

I_OUT = 500 mA

C_OUT= 1 µF

Figure 55. LP5912-1.8 V_OUT vs V_EN (ON)

V_IN = 2.3 V

I_OUT = 500 mA (3.6 Ω)

C_OUT= 1 µF

Figure 56. LP5912-1.8 V_OUT vs V_EN (OFF)

10 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must be well regulated and free of spurious noise. To ensure that the LP5912-Q1 output voltage is well regulated and dynamic performance is optimum, the input supply must be at least V_OUT + 0.5 V. A minimum capacitor value of 1 µF is required to be within 1 cm of the IN pin.

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP5912-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912-Q1.

Best performance is achieved by placing C_IN and C_OUT on the same side of the PCB as the LP5912-Q1, and as close to the package as is practical. The ground connections for C_IN and C_OUT must be back to the LP5912-Q1 ground pin using as wide and as short of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such connections add parasitic inductances and resistance that result in inferior performance especially during transient conditions.

11.2 Layout Example

Figure 57. LP5912-Q1 Typical Layout