ZHCSFN1A November   2016  – January 2022 UCC20520

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表

Layout Guidelines

To achieve optimum performance for the UCC20520, pay close attention to PCB layout in order.

Component Placement:

  • Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
  • To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
  • It is recommended to place the dead time setting resistor, RDT, and its bypassing capacitor close to DT pin of UCC20520.

Grounding Considerations:

  • It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
  • Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

  • To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the UCC20520’s isolation performance.
  • For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB layout between the high and low-side PCB traces.

Thermal Considerations:

  • A large amount of power may be dissipated by the UCC20520 if the driving voltage is high, the load is heavy, or the switching frequency is high (Refer to Section 9.2.2.4 for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
  • Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended (See Figure 10-2 and Figure 10-3). However, high voltage PCB considerations mentioned above must be maintained.
  • If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind that there shouldn’t be any traces/coppers from different high voltage planes overlapping.