ZHCSFH1 September   2016 LMK04208

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1  System Architecture
      2. 8.1.2  PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      3. 8.1.3  PLL1 Tunable Crystal Support
      4. 8.1.4  VCXO/Crystal Buffered Output
      5. 8.1.5  Frequency Holdover
      6. 8.1.6  Integrated Loop Filter Poles
      7. 8.1.7  Internal VCO
      8. 8.1.8  External VCO Mode
      9. 8.1.9  Clock Distribution
        1. 8.1.9.1 CLKout DIVIDER
        2. 8.1.9.2 CLKout Delay
        3. 8.1.9.3 Programmable Output Type
        4. 8.1.9.4 Clock Output Synchronization
      10. 8.1.10 0-Delay
      11. 8.1.11 Default Startup Clocks
      12. 8.1.12 Status Pins
      13. 8.1.13 Register Readback
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs / Outputs
        1. 8.3.1.1 PLL1 Reference Inputs (CLKin0 and CLKin1)
        2. 8.3.1.2 PLL2 OSCin / OSCin* Port
        3. 8.3.1.3 Crystal Oscillator
      2. 8.3.2 Input Clock Switching
        1. 8.3.2.1 Input Clock Switching - Manual Mode
        2. 8.3.2.2 Input Clock Switching - Pin Select Mode
          1. 8.3.2.2.1 Pin Select Mode and Host
          2. 8.3.2.2.2 Switch Event without Holdover
          3. 8.3.2.2.3 Switch Event with Holdover
        3. 8.3.2.3 Input Clock Switching - Automatic Mode
          1. 8.3.2.3.1 Starting Active Clock
          2. 8.3.2.3.2 Clock Switch Event: PLL1 DLD
          3. 8.3.2.3.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.2.3.4 Clock Switch Event with Holdover
        4. 8.3.2.4 Input Clock Switching - Automatic Mode with Pin Select
          1. 8.3.2.4.1 Starting Active Clock
          2. 8.3.2.4.2 Clock Switch Event: PLL1 DLD
          3. 8.3.2.4.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.2.4.4 Clock Switch Event with Holdover
      3. 8.3.3 Holdover Mode
        1. 8.3.3.1 Enable Holdover
        2. 8.3.3.2 Entering Holdover
        3. 8.3.3.3 During Holdover
        4. 8.3.3.4 Exiting Holdover
        5. 8.3.3.5 Holdover Frequency Accuracy and DAC Performance
        6. 8.3.3.6 Holdover Mode - Automatic Exit of Holdover
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL1
        2. 8.3.4.2 PLL2
          1. 8.3.4.2.1 PLL2 Frequency Doubler
        3. 8.3.4.3 Digital Lock Detect
      5. 8.3.5 Status Pins
        1. 8.3.5.1 Logic Low
        2. 8.3.5.2 Digital Lock Detect
        3. 8.3.5.3 Holdover Status
        4. 8.3.5.4 DAC
        5. 8.3.5.5 PLL Divider Outputs
        6. 8.3.5.6 CLKinX_LOS
        7. 8.3.5.7 CLKinX Selected
        8. 8.3.5.8 MICROWIRE Readback
      6. 8.3.6 VCO
      7. 8.3.7 Clock Distribution
        1. 8.3.7.1 Fixed Digital Delay
        2. 8.3.7.2 Fixed Digital Delay - Example
        3. 8.3.7.3 Clock Output Synchronization (SYNC)
          1. 8.3.7.3.1 Effect of SYNC
          2. 8.3.7.3.2 Methods of Generating SYNC
          3. 8.3.7.3.3 Avoiding Clock Output Interruption Due to Sync
          4. 8.3.7.3.4 SYNC Timing
        4. 8.3.7.4 Dynamically Programming Digital Delay
          1. 8.3.7.4.1 Absolute vs. Relative Dynamic Digital Delay
          2. 8.3.7.4.2 Dynamic Digital Delay and 0-Delay Mode
          3. 8.3.7.4.3 SYNC and Minimum Step Size
          4. 8.3.7.4.4 Programming Overview
          5. 8.3.7.4.5 Internal Dynamic Digital Delay Timing
          6. 8.3.7.4.6 Other Timing Requirements
        5. 8.3.7.5 Absolute Dynamic Digital Delay
          1. 8.3.7.5.1 Absolute Dynamic Digital Delay - Example
        6. 8.3.7.6 Relative Dynamic Digital Delay
          1. 8.3.7.6.1 Relative Dynamic Digital Delay - Example
      8. 8.3.8 0-Delay Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Selection
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Dual PLL
        2. 8.4.2.2 0-Delay Dual PLL
        3. 8.4.2.3 Single PLL
        4. 8.4.2.4 0-Delay Single PLL
        5. 8.4.2.5 Clock Distribution
    5. 8.5 Programming
      1. 8.5.1 Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY
        1. 8.5.1.1 Example
      2. 8.5.2 Recommended Programming Sequence
        1. 8.5.2.1 Programming Sequence Overview
      3. 8.5.3 Readback
        1. 8.5.3.1 Readback - Example
    6. 8.6 Register Maps
      1. 8.6.1 Register Map and Readback Register Map
      2. 8.6.2 Default Device Register Settings After Power On Reset
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1  Registers R0 to R5
          1. 8.6.3.1.1 CLKoutX_PD, Powerdown CLKoutX Output Path
          2. 8.6.3.1.2 CLKoutX_OSCin_Sel, Clock Group Source
          3. 8.6.3.1.3 CLKoutX_ADLY_SEL, Select Analog Delay
          4. 8.6.3.1.4 CLKoutX_DDLY, Clock Channel Digital Delay
          5. 8.6.3.1.5 Reset
          6. 8.6.3.1.6 POWERDOWN
          7. 8.6.3.1.7 CLKoutX_HS, Digital Delay Half Shift
          8. 8.6.3.1.8 CLKoutX_DIV, Clock Output Divide
        2. 8.6.3.2  Registers R6 to R8
          1. 8.6.3.2.1 CLKoutX_TYPE
          2. 8.6.3.2.2 CLKoutX_ADLY
        3. 8.6.3.3  Register R10
          1. 8.6.3.3.1 OSCout_TYPE
          2. 8.6.3.3.2 EN_OSCout, OSCout Output Enable
          3. 8.6.3.3.3 OSCout_MUX, Clock Output Mux
          4. 8.6.3.3.4 PD_OSCin, OSCin Powerdown Control
          5. 8.6.3.3.5 OSCout_DIV, Oscillator Output Divide
          6. 8.6.3.3.6 VCO_MUX
          7. 8.6.3.3.7 EN_FEEDBACK_MUX
          8. 8.6.3.3.8 VCO_DIV, VCO Divider
          9. 8.6.3.3.9 FEEDBACK_MUX
        4. 8.6.3.4  Register R11
          1. 8.6.3.4.1 MODE: Device Mode
          2. 8.6.3.4.2 EN_SYNC, Enable Synchronization
          3. 8.6.3.4.3 NO_SYNC_CLKoutX
          4. 8.6.3.4.4 SYNC_MUX
          5. 8.6.3.4.5 SYNC_QUAL
          6. 8.6.3.4.6 SYNC_POL_INV
          7. 8.6.3.4.7 SYNC_EN_AUTO
          8. 8.6.3.4.8 SYNC_TYPE
          9. 8.6.3.4.9 EN_PLL2_XTAL
        5. 8.6.3.5  Register R12
          1. 8.6.3.5.1 LD_MUX
          2. 8.6.3.5.2 LD_TYPE
          3. 8.6.3.5.3 SYNC_PLLX_DLD
          4. 8.6.3.5.4 EN_TRACK
          5. 8.6.3.5.5 HOLDOVER_MODE
        6. 8.6.3.6  Register R13
          1. 8.6.3.6.1 HOLDOVER_MUX
          2. 8.6.3.6.2 HOLDOVER_TYPE
          3. 8.6.3.6.3 Status_CLKin1_MUX
          4. 8.6.3.6.4 Status_CLKin0_TYPE
          5. 8.6.3.6.5 DISABLE_DLD1_DET
          6. 8.6.3.6.6 Status_CLKin0_MUX
          7. 8.6.3.6.7 CLKin_SELECT_MODE
          8. 8.6.3.6.8 CLKin_Sel_INV
          9. 8.6.3.6.9 EN_CLKinX
        7. 8.6.3.7  Register 14
          1. 8.6.3.7.1 LOS_TIMEOUT
          2. 8.6.3.7.2 EN_LOS
          3. 8.6.3.7.3 Status_CLKin1_TYPE
          4. 8.6.3.7.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type
          5. 8.6.3.7.5 DAC_HIGH_TRIP
          6. 8.6.3.7.6 DAC_LOW_TRIP
          7. 8.6.3.7.7 EN_VTUNE_RAIL_DET
        8. 8.6.3.8  Register 15
          1. 8.6.3.8.1 MAN_DAC
          2. 8.6.3.8.2 EN_MAN_DAC
          3. 8.6.3.8.3 HOLDOVER_DLD_CNT
          4. 8.6.3.8.4 FORCE_HOLDOVER
        9. 8.6.3.9  Register 16
          1. 8.6.3.9.1 XTAL_LVL
        10. 8.6.3.10 Register 23
          1. 8.6.3.10.1 DAC_CNT
        11. 8.6.3.11 Register 24
          1. 8.6.3.11.1 PLL2_C4_LF, PLL2 Integrated Loop Filter Component
          2. 8.6.3.11.2 PLL2_C3_LF, PLL2 Integrated Loop Filter Component
          3. 8.6.3.11.3 PLL2_R4_LF, PLL2 Integrated Loop Filter Component
          4. 8.6.3.11.4 PLL2_R3_LF, PLL2 Integrated Loop Filter Component
          5. 8.6.3.11.5 PLL1_N_DLY
          6. 8.6.3.11.6 PLL1_R_DLY
          7. 8.6.3.11.7 PLL1_WND_SIZE
        12. 8.6.3.12 Register 25
          1. 8.6.3.12.1 DAC_CLK_DIV
          2. 8.6.3.12.2 PLL1_DLD_CNT
        13. 8.6.3.13 Register 26
          1. 8.6.3.13.1 PLL2_WND_SIZE
          2. 8.6.3.13.2 EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler
          3. 8.6.3.13.3 PLL2_CP_POL, PLL2 Charge Pump Polarity
          4. 8.6.3.13.4 PLL2_CP_GAIN, PLL2 Charge Pump Current
          5. 8.6.3.13.5 PLL2_DLD_CNT
          6. 8.6.3.13.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE
        14. 8.6.3.14 Register 27
          1. 8.6.3.14.1 PLL1_CP_POL, PLL1 Charge Pump Polarity
          2. 8.6.3.14.2 PLL1_CP_GAIN, PLL1 Charge Pump Current
          3. 8.6.3.14.3 CLKinX_PreR_DIV
          4. 8.6.3.14.4 PLL1_R, PLL1 R Divider
          5. 8.6.3.14.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE
        15. 8.6.3.15 Register 28
          1. 8.6.3.15.1 PLL2_R, PLL2 R Divider
          2. 8.6.3.15.2 PLL1_N, PLL1 N Divider
        16. 8.6.3.16 Register 29
          1. 8.6.3.16.1 OSCin_FREQ, PLL2 Oscillator Input Frequency Register
          2. 8.6.3.16.2 PLL2_FAST_PDF, High PLL2 Phase Detector Frequency
          3. 8.6.3.16.3 PLL2_N_CAL, PLL2 N Calibration Divider
        17. 8.6.3.17 Register 30
          1. 8.6.3.17.1 PLL2_P, PLL2 N Prescaler Divider
          2. 8.6.3.17.2 PLL2_N, PLL2 N Divider
        18. 8.6.3.18 Register 31
          1. 8.6.3.18.1 READBACK_LE
          2. 8.6.3.18.2 READBACK_ADDR
          3. 8.6.3.18.3 uWire_LOCK
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter
        1. 9.1.1.1 PLL1
        2. 9.1.1.2 PLL2
      2. 9.1.2 Driving CLKin and OSCin Inputs
        1. 9.1.2.1 Driving CLKin Pins with a Differential Source
        2. 9.1.2.2 Driving CLKin Pins with a Single-Ended Source
      3. 9.1.3 Termination and Use of Clock Output (Drivers)
        1. 9.1.3.1 Termination for DC Coupled Differential Operation
        2. 9.1.3.2 Termination for AC Coupled Differential Operation
        3. 9.1.3.3 Termination for Single-Ended Operation
      4. 9.1.4 Frequency Planning with the LMK04208
      5. 9.1.5 PLL Programming
        1. 9.1.5.1 Example PLL2 N Divider Programming
      6. 9.1.6 Digital Lock Detect Frequency Accuracy
        1. 9.1.6.1 Minimum Lock Time Calculation Example
      7. 9.1.7 Calculating Dynamic Digital Delay Values for Any Divide
        1. 9.1.7.1 Example
      8. 9.1.8 Optional Crystal Oscillator Implementation (OSCin/OSCin*)
        1. 9.1.8.1 Examples of Phase Noise and Jitter Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
          2. 9.2.2.1.2 Calculation Using LCM
        2. 9.2.2.2 Device Configuration
          1. 9.2.2.2.1 PLL LO Reference
          2. 9.2.2.2.2 POR Clock
        3. 9.2.2.3 PLL Loop Filter Design
          1. 9.2.2.3.1 PLL1 Loop Filter Design
          2. 9.2.2.3.2 PLL2 Loop Filter Design
        4. 9.2.2.4 Clock Output Assignment
        5. 9.2.2.5 Other Device Specific Configuration
          1. 9.2.2.5.1 Digital Lock Detect
          2. 9.2.2.5.2 Holdover
        6. 9.2.2.6 Device Programming
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 System Level Diagram
    4. 9.4 Do's and Don'ts
      1. 9.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 9.4.2 LVPECL Outputs
      3. 9.4.3 Sharing MICROWIRE (SPI) Lines
  10. 10Power Supply Recommendations
    1. 10.1 Pin Connection Recommendations
      1. 10.1.1 Vcc Pins and Decoupling
        1. 10.1.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
        2. 10.1.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
        3. 10.1.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
        4. 10.1.1.4 Vcc5 (CLKin), Vcc7 (OSCin and OSCout)
      2. 10.1.2 LVPECL Outputs
      3. 10.1.3 Unused Clock Outputs
      4. 10.1.4 Unused Clock Inputs
      5. 10.1.5 LDO Bypass
    2. 10.2 Current Consumption and Power Dissipation Calculations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

To assist customers in frequency planning and design of loop filters, Texas Instruments provides Clock Architect.

9.1.1 Loop Filter

Each PLL of the LMK04208 requires a dedicated loop filter.

LMK04208 PLL1_and_PLL2_Loop_filters_updated1302015_snas489.gif Figure 21. PLL1 and PLL2 Loop Filters

9.1.1.1 PLL1

The loop filter for PLL1 must be connected to the CPout1 pin. Figure 21 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO module or discrete implementation of a VCXO using a crystal resonator and external varactor diode. Higher order loop filters may be implemented using additional external R and C components. TI recommends that the loop filter for PLL1 result in a total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and phase detector frequency for PLL1. TI's Clock Conditioner Owner’s Manual covers this topic in detail and Texas Instruments Clock Architect can be used to simulate loop filter designs for both PLLs. These resources may be found at:

Clock and Timing landing page.

9.1.1.2 PLL2

As shown in Figure 21, the charge pump for PLL2 is directly connected to the optional internal loop filter components, which are normally used only if either a third or fourth pole is needed. The first and second poles are implemented with external components. The loop must be designed to be stable over the entire application-specific tuning range of the VCO. The designer should note the range of KVCO listed in the table of Electrical Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because loop bandwidth is directly proportional to KVCO, the designer should model and simulate the loop at the expected extremes of the desired tuning range, using the appropriate values for KVCO.

When designing with the integrated loop filter of the LMK04208, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4.

Both the integrated loop filter resistors (R3 and R4) and capacitors (C3 and C4) also restrict the maximum loop bandwidth. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In situations where spur requirements are very stringent and there is margin on phase noise, a feasible strategy would be to design a loop filter with integrated resistor values larger than their minimum value.

9.1.2 Driving CLKin and OSCin Inputs

9.1.2.1 Driving CLKin Pins with a Differential Source

Both CLKin ports can be driven by differential signals. TI recommends that the input mode be set to bipolar (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04208 internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 22 and Figure 23.

LMK04208 CLKinX_X_Termination_LVDS_Reference_Clock_Source.gif Figure 22. CLKinX/X* Termination for an LVDS Reference Clock Source
LMK04208 CLKinX_X_Termination_LVPECL_Reference_Clock_Source.gif Figure 23. CLKinX/X* Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics.

LMK04208 termination_differential_sine_wave.gif Figure 24. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source

9.1.2.2 Driving CLKin Pins with a Single-Ended Source

The CLKin pins of the LMK04208 can be driven using a single-ended reference clock source, for example, either a sine wave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends that AC coupling be used as shown in Figure 25 with a 50-Ω termination.

NOTE

The signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics. CLKinX_BUF_TYPE in Register 11 is recommended to be set to bipolar mode (CLKinX_BUF_TYPE = 0).

LMK04208 CLKIN_X_X_single_ended_termination.gif Figure 25. CLKinX/X* Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient.

LMK04208 CLKinX_X_Single_ended_Termination.gif Figure 26. DC Coupled LVCMOS/LVTTL Reference Clock

9.1.3 Termination and Use of Clock Output (Drivers)

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

  • Transmission line theory should be followed for good impedance matching to prevent reflections.
  • Clock drivers should be presented with the proper loads. For example:
    • LVDS drivers are current drivers and require a closed current loop.
    • LVPECL drivers are open emitters and require a DC path to ground.
  • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled.

It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK04208 , OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 40) This is only slightly different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage), not the driver.

9.1.3.1 Termination for DC Coupled Differential Operation

For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 27.

LMK04208 30102320.gif Figure 27. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver

For DC coupled operation of an LVPECL driver, terminate with 50 Ω to VCC - 2 V as shown in Figure 28. Alternatively, terminate with a Thevenin equivalent circuit (120-Ω resistor connected to VCC and an 82-Ω resistor connected to ground with the driver connected to the junction of the 120-Ω and 82-Ω resistors) as shown in Figure 29 for VCC = 3.3 V.

LMK04208 30102318.gif Figure 28. Differential LVPECL Operation, DC Coupling
LMK04208 30102321.gif Figure 29. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent

9.1.3.2 Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level.

When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 30.

LMK04208 30102319.gif Figure 30. Differential LVDS Operation, AC Coupling,
External Biasing at the Receiver

Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 30 is modified by replacing the 50-Ω terminations to Vbias with a single 100-Ω resistor across the input pins of the receiver, as shown in Figure 31. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous figures employ a 0.10-µF capacitor. This value may need to be adjusted to meet the startup requirements for a particular application.

LMK04208 30102382.gif Figure 31. LVDS Termination for a Self-Biased Receiver

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120-Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 32. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82-Ω resistor connected to VCC and a 120-Ω resistor connected to ground with the driver connected to the junction of the 82-Ω and 120-Ω resistors) is a valid termination as shown in Figure 32 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 29.

LMK04208 30102317.gif Figure 32. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent,
External Biasing at the Receiver

9.1.3.3 Termination for Single-Ended Operation

A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When DC coupling one of the LMK04208 clock LVPECL drivers, the termination should be 50 Ω to VCC - 2 V as shown in Figure 33. The Thevenin equivalent circuit is also a valid termination as shown in Figure 34 for Vcc = 3.3 V.

LMK04208 30102315.gif Figure 33. Single-Ended LVPECL Operation, DC Coupling
LMK04208 30102316.gif Figure 34. Single-Ended LVPECL Operation, DC Coupling,
Thevenin Equivalent

When AC coupling an LVPECL driver use a 120-Ω emitter resistor to provide a DC path to ground and ensure a 50-Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50-Ω termination of the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 35.

LMK04208 30102314.gif Figure 35. Single-Ended LVPECL Operation, AC Coupling

9.1.4 Frequency Planning with the LMK04208

Calculating the value of the output dividers for use with the LMK04208 is simple due to the architecture of the LMK04208. That is, the VCO divider may be bypassed and the clock output dividers allow for even and odd output divide values from 2 to 1045. For most applications, TI recommends bypassing the VCO divider.

The procedure for determining the needed LMK04208 device and clock output divider values for a set of clock output frequencies is straightforward.

  1. Calculate the least common multiple (LCM) of the clock output frequencies.
  2. Determine which VCO ranges will support the target clock output frequencies given the LCM.
  3. Determine the clock output divide values based on VCO frequency.
  4. Determine the PLL2_P, PLL2_N, and PLL2_R divider values given the OSCin VCXO or crystal frequency and VCO frequency.

For example, given the following target output frequencies: 200 MHz, 120 MHz, and 25 MHz with a VCXO frequency of 40 MHz:

  • First determine the LCM of the three frequencies. LCM(200 MHz, 120 MHz, 25 MHz) = 600 MHz. The LCM frequency is the lowest frequency for which all of the target output frequencies are integer divisors of the LCM. Note: if there is one frequency which causes the LCM to be very large, greater than 3 GHz for example, determine if there is a single frequency requirement which causes this. It may be possible to select the VCXO/crystal frequency to satisfy this frequency requirement through OSCout or CLKout3/4 driven by OSCin. In this way it is possible to get non-integer related frequencies at the outputs.
  • Second, since the LCM is not in a VCO frequency range supported by the LMK04208, multiply the LCM frequency by an integer which causes it to fall into a valid VCO frequency range of an LMK04208 device. In this case 600 MHz * 5 = 3000 MHz which is valid for the LMK04208.
  • Third, continuing the example by using a VCO frequency of 3000 MHz and the LMK04208, the CLKout dividers can be calculated by simply dividing the VCO frequency by the output frequency. To output 200 MHz, 120 MHz, and 25 MHz the output dividers will be 12, 20, and 96 respectively.
    • 3000 MHz / 200 MHz = 15
    • 3000 MHz / 120 MHz = 25
    • 3000 MHz / 25 MHz = 120
  • Fourth, PLL2 must be locked to its input reference. Refer to PLL Programming for more information on this topic. By programming the clock output dividers and the PLL2 dividers the VCO can lock to the frequency of 3000 MHz and the clock outputs dividers will each divide the VCO frequency down to the target output frequencies of 200 MHz, 120 MHz, and 25 MHz.

Refer to AN-1865, Frequency Synthesis and Planning for PLL Architectures for more information on this topic and LCM calculations.

9.1.5 PLL Programming

To lock a PLL the divided reference and divided feedback from VCO or VCXO must result in the same phase detector frequency. The tables below illustrate how the divides are structured for the reference path (R) and feedback path (N) depending on the MODE of the device.

Table 109. PLL1 Phase Detector Frequency — Reference Path (R)

MODE PLL1 PDF (R) =
All CLKinX Frequency / (CLKinX_PreR_DIV * PLL1_R)

Table 110. PLL1 Phase Detector Frequency — Feedback Path (N)

MODE VCO_MUX OSCout PLL1 PDF (N) =
Dual PLL, Internal VCO Bypass VCXO Frequency / PLL1_N
Divided VCXO Frequency / (OSCin_DIV * PLL1_N)
Dual PLL, Internal VCO, 0-Delay Bypass VCO Frequency / (CLKoutX_DIV * PLL1_N) (1)
Divided VCO Frequency / (VCO_DIV * CLKoutX_DIV * PLL1_N) (1)
Dual PLL, External VCO, 0-Delay VCO Frequency / (CLKoutX_DIV * PLL1_N) (1)
(1) The actual CLKoutX_DIV used is selected by the feedback mux. See EN_FEEDBACK_MUX.

Table 111. PLL2 Phase Detector Frequency — Reference Path (R)

EN_PLL2_REF_2X PLL2 PDF (R) =
Disabled OSCin Frequency / PLL2_R(1)(2)
Enabled OSCin Frequency * 2 / PLL2_R(1)(2)
(1) For applications in which the OSCin frequency and PLL2 phase detector frequency are equal, the best PLL2 in-band noise can be achieved when the doubler is enabled (EN_PLL2_REF_2X = 1) and the PLL2 R divide value is 2. Do not use doubler disabled (EN_PLL2_REF_2X = 0) and PLL2 R divide value of 1.

Table 112. PLL2 Phase Detector Frequency — Feedback Path (N)

MODE VCO_MUX PLL2 PDF (N) =
Dual PLL, Internal VCO VCO VCO Frequency / (PLL2_P * PLL2_N)
Dual PLL, Internal VCO, 0-Delay
Single PLL, Internal VCO
Dual PLL, Internal VCO VCO Divider VCO Frequency / (VCO_DIV * PLL2_P * PLL2_N)
Dual PLL, Internal VCO, 0-Delay
Single PLL, Internal VCO
Dual PLL, External VCO VCO Frequency / (PLL2_P * PLL2_N)
Dual PLL External VCO, 0-Delay
Single PLL, External VCO
Single PLL, Internal VCO, 0-Delay VCO VCO Frequency / (CLKoutX_DIV * PLL2_N)
VCO Divider VCO Frequency / (VCO_DIV * CLKoutX_DIV * PLL2_N)

Table 113. PLL2 Phase Detector Frequency — Feedback Path (N) During VCO Frequency Calibration

MODE VCO_MUX PLL2 PDF (N_CAL) =
All Internal VCO Modes VCO VCO Frequency / (PLL2_P * PLL2_N_CAL)
VCO Divider VCO Frequency / (VCO_DIV * PLL2_P * PLL2_N_CAL)

9.1.5.1 Example PLL2 N Divider Programming

To program PLL2 to lock an LMK04208 using Dual PLL mode to a VCO frequency of 3000 MHz using a 40 MHz VCXO reference, first determine the total PLL2 N divide value. This is VCO Frequency / PLL2 phase detector frequency. This example assumes the PLL2 reference frequency doubler is enabled and a PLL2 R divide value of 2 (see Note 1 in Table 111) which results in PLL2 phase detector frequency the same as PLL2 reference frequency (40 MHz). 3000 MHz / 40 MHz = 75, so the total PLL2 N divide value is 75.

The dividers in the PLL2 N feedback path for Dual PLL mode include PLL2_P and PLL2_N. PLL2_P can be programmed from 2 to 8, including both even and odd values. PLL2_N can be programmed from 1 to 263,143, including both even and odd values. Since the total PLL2 N divide value of 75 contains the factors 3, 5, and 5, it would be allowable to program PLL2_P to 3 or 5. It is simplest to use the smallest divide, so PLL2_P = 3, and PLL2_N = 25 which results in a Total PLL2 N = 75.

For this example and in most cases, PLL2_N_CAL will have the same value as PLL2_N. However when using Single PLL mode with 0-delay, the values will differ. When using an external VCO, PLL2_N_CAL value is unused.

9.1.6 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true. When the holdover exit event occurs, the device will exit holdover mode.

Table 114. Digital Lock Detect Frequency Accuracy Table

EVENT PLL WINDOW SIZE LOCK COUNT
PLL1 Locked PLL1 PLL1_WND_SIZE PLL1_DLD_CNT
PLL2 Locked PLL2 PLL2_WND_SIZE PLL2_DLD_CNT
Holdover exit PLL1 PLL1_WND_SIZE HOLDOVER_DLD_CNT

For a digital lock detect event to occur there must be a “lock count” number of phase detector cycles of PLLX during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable "window size." Since there must be at least "lock count" phase detector events before a lock event occurs, a minimum digital lock event time can be calculated as "lock count" / fPDX where X = 1 for PLL1 or 2 for PLL2.

By using Equation 5, values for a "lock count" and "window size" can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs:

Equation 5. LMK04208 30102362.gif

The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock count".

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window size", then the “lock count” value is reset to 0.

9.1.6.1 Minimum Lock Time Calculation Example

The minimum time for PLL2 digital lock to be asserted can be calculated by Equation 6:

Equation 6. PLL2_DLD_CNT / Phase detector frequency

Given a PLL2 phase detector frequency of 40 MHz and PLL2_DLD_CNT value of 10,000, the minimum digital lock detect time of PLL2 will be 10,000 / 40 MHz = 250 μs.

9.1.7 Calculating Dynamic Digital Delay Values for Any Divide

This section explains how to calculate the dynamic digital delay for any divide value.

Dynamic digital delay allows the time offset between two or more clock outputs to be adjusted with no or minimal interruption of clock outputs. Since the clock outputs are operating at a known frequency, the time offset can also be expressed as a phase shift. When dynamically adjusting the digital delay of clock outputs with different frequencies the phase shift should be expressed in terms of the higher frequency clock. The step size of the smallest time adjustment possible is equal to half the period of the Clock Distribution Path, which is the VCO frequency (Equation 3) or the VCO frequency divided by the VCO divider (Equation 4) if not bypassed. The smallest degree phase adjustment with respect to a clock frequency will be 360 * the smallest time adjustment * the clock frequency. The total number of phase offsets that the LMK04208 is able to achieve using dynamic digital delay is equal 1 / (higher clock frequency * the smallest phase adjustment).

Equation 7 calculates the digital delay value that must be programmed for a synchronizing clock to achieve a 0 time/phase offset from the qualifying clock. Once this digital delay value is known, it is possible to calculate the digital delay value for any phase offset. The qualifying clock for dynamic digital delay is selected by the FEEDBACK_MUX. When dynamic digital delay is engaged with same clock output used for the qualifying clock and the new synchronized clock, it is termed relative dynamic digital delay since causing another SYNC event with the same digital delay value will offset the clock by the same phase once again. The important part of relative dynamic digital delay is that the CLKoutX_HS must be programmed correctly when the SYNC event occurs (Table 6). This can result in needing to program the device twice. Once to set the new CLKoutX_DDLY with CLKoutX_HS as required for the SYNC event, and again to set the CLKoutX_HS to its desired value.

Digital delay values are programmed using the CLKoutX_DDLY and CLKoutX_HS registers as shown in Equation 8. For example, to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1.

Equation 7. LMK04208 30102358.gif

Equation 7 uses the ceiling operator. To find the ceiling of a fractional number round up. An integer remains the same value.

Equation 8. Digital delay = CLKoutX_DDLY - (0.5 * CLKoutX_HS)

Note: since the digital delay value for 0 time/phase offset is a function of the qualifying clock's divide value, the resulting digital delay value can be used for any clock output operating at any frequency to achieve a 0 time/phase offset from the qualifying clock. Therefore the calculated time shift table will also be the same as in Table 115.

9.1.7.1 Example

Consider a system with:

  • A VCO frequency of 3000 MHz.
  • The VCO divider is bypassed, therefore the clock distribution path frequency is 3000 MHz.
  • CLKout0_DIV = 10 resulting in a 300 MHz frequency on CLKout0.
  • CLKout1_DIV = 20 resulting in a 150 MHz frequency on CLKout2.

For this system the minimum time adjustment is ~0.16667 ns, which is 0.5 / (3000 MHz). Since the higher frequency is 300 MHz, phase adjustments will be calculated with respect to the 300 MHz frequency. The 0.25 ns minimum time adjustment results in a minimum phase adjustment of 18 degrees, which is 360 degrees / 200 MHz * 0.25 ns.

To calculate the digital delay value to achieve a 0 time/phase shift of CLKout2 when CLKout0 is the qualifying clock. Solve Equation 7 using the divide value of 10. To solve the equation 16/10 = 1.6, the ceiling of 1.6 is 2. Then to finish solving the equation solve (2 + 0.5) * 10 - 11.5 = 13.5. A digital delay value of 13.5 is programmed by setting CLKout1_DDLY = 14 and CLKout1_HS = 1.

To calculate the digital delay value to achieve a 0 time/phase shift of CLKout0 when CLKout2 is the qualifying clock, solve Equation 7 using the divide value of CLKout2, which is 20. This results in a digital delay of 18.5 which is programmed as CLKout0_DDLY = 19 and CLKout0_HS = 1.

Once the 0 time/phase shift digital delay programming value is known a table can be constructed with the digital delay value to be programmed for any time/phase offset by decrementing or incrementing the digital delay value by 0.5 for the minimum time/phase adjustment.

A complete filled out table for use of CLKout0 as the qualifying clock is shown in Table 115. It was created by entering a digital delay of 13.5 for 0 degree phase shift, then decrementing the digital delay down to the minimum value of 4.5. Since this did not result in all the possible phase shifts, the digital delay was then incremented from 13.5 to 14.0 to complete all possible phase shifts.

Table 115. Example Digital Delay Calculation

DIGITAL DELAY
CALCULATED TIME SHIFT
(ns)
RELATIVE TIME SHIFT
to 300 MHz (ns)
PHASE SHIFT
of 300 MHz (Degrees)
4.5 -3.0 0.333... 36
5 -2.833... 0.5 54
5.5 -2.666... 0.666... 72
6 -2.5 0.833... 90
6.5 -2.333 1.0 108
7 -2.166 1.166... 126
7.5 -2.0 1.333... 144
8 -1.833 1.5 162
8.5 -1.666... 1.666... 180
9 -1.5 1.833... 198
9.5 -1.333... 2.0 216
10 -1.166... 2.166... 234
10.5 -1.0 2.333... 252
11 -0.833... 2.5 270
11.5 -0.666... 2.666... 288
12 -0.5 2.833... 306
12.5 -0.333... 3.0 324
13 -0.166... 3.166... 342
13.5 0 0 0
14 0.166... 0.166... 18
14.5 0.333... 0.333... 36

Observe that the digital delay value of 4.5 and 14.5 will achieve the same relative time shift/phase delay. However programming a digital delay of 14.5 will result in a clock off time for the synchronizing clock to achieve the same phase time shift/phase delay.

Digital delay value is programmed as CLKoutX_DDLY - (0.5 * CLKoutX_HS). So to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1. To achieve a digital delay of 14, program CLKoutX_DDLY = 14 and CLKoutX_HS = 0.

9.1.8 Optional Crystal Oscillator Implementation (OSCin/OSCin*)

The LMK04208 features supporting circuitry for a discretely implemented oscillator driving the OSCin port pins. Figure 36 illustrates a reference design circuit for a crystal oscillator:

LMK04208 30102363.gif Figure 36. Reference Design Circuit for Crystal Oscillator Option

This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel resonance, the total load capacitance, CL, must be specified. The load capacitance is the sum of the tuning capacitance (CTUNE), the capacitance seen looking into the OSCin port (CIN), and stray capacitance due to PCB parasitics (CSTRAY), and is given by Equation 9.

Equation 9. LMK04208 30102364.gif

CTUNE is provided by the varactor diode shown in Figure 36, Skyworks model SMV1249-074LF. A dual diode package with common cathode provides the variable capacitance for tuning. The single diode capacitance ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The typical performance curve from the data sheet for the SMV1249-074LF indicates that the capacitance at this voltage is approximately 6 pF (12 pF / 2).

The nominal input capacitance (CIN) of the LMK04208 OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as possible and as narrow as possible trace width (50 Ω characteristic impedance is not required).

As an example, assume that CSTRAY is 4 pF. The total load capacitance is nominally:

Equation 10. LMK04208 30102365.gif

Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF.

The 2.2-nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the 4.7-kΩ and 10-kΩ resistors. The value of these coupling capacitors should be large, relative to the value of CTUNE (CC1 = CC2 >> CTUNE), so that CTUNE becomes the dominant capacitance.

For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is:

Equation 11. LMK04208 30102366.gif

where

  • FS = Series resonant frequency
  • C1 = Motional capacitance of the crystal
  • CL = Load capacitance
  • C0 = Shunt capacitance of the crystal, specified on the crystal datasheet

The normalized tuning range of the circuit is closely approximated by:

Equation 12. LMK04208 30102367.gif

CL1, CL2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit’s load capacitance range.

A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning range because this allows the scale factors related to the load capacitance to dominate.

9.1.8.1 Examples of Phase Noise and Jitter Performance

Examples of the phase noise and jitter performance of the LMK04208 with a crystal oscillator are shown in Table 116. This table illustrates the clock output phase noise when a 20.48-MHz crystal is paired with PLL1. Performance of other LMK04208 devices will be similar.

Table 116. Example RMS Jitter and Clock Output Phase Noise for LMK04208
with a 20.48 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (1)

INTEGRATION BANDWIDTH CLOCK OUTPUT TYPE PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0, XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz fCLK = 122.88 MHz fCLK = 245.76 MHz
RMS JITTER (fs, RMS)
100 Hz – 20 MHz LVCMOS 374 412 382
LVDS 419 421 372
LVPECL 1.6 Vpp 460 448 440
10 kHz – 20 MHz LVCMOS 226 195 190
LVDS 231 205 194
LVPECL 1.6 Vpp 226 191 188
PHASE NOISE (dBc/Hz)
Offset Clock Output Type PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0, XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz fCLK = 122.88 MHz fCLK = 245.76 MHz
100 Hz LVCMOS -87 -93 -87
LVDS -86 -91 -86
LVPECL 1.6 Vpp -86 -92 -85
1 kHz LVCMOS -115 -121 -115
LVDS -115 -123 -116
LVPECL 1.6 Vpp -114 -122 -116
10 kHz LVCMOS -117 -128 -122
LVDS -117 -128 -122
LVPECL 1.6 Vpp -117 -128 -122
100 kHz LVCMOS -130 -135 -129
LVDS -130 -135 -129
LVPECL 1.6 Vpp -129 -135 -129
1 MHz LVCMOS -150 -154 -148
LVDS -149 -153 -148
LVPECL 1.6 Vpp -150 -154 -148
40 MHz LVCMOS -159 -162 -159
LVDS -157 -159 -157
LVPECL 1.6 Vpp -159 -161 -159
(1) Performance data and crystal specifications contained in this section are based on Vectron model VXB1-1150-20M480, 20.48 MHz. PLL1 has a narrow loop bandwidth, PLL2 loop parameters are: C1 = 150 pF, C2 = 120 nF, R2 = 470 Ω, Charge Pump current = 3.2 mA, Phase detector frequency = 20.48 MHz or 40.96 MHz, VCO frequency = 2949.12 MHz. Loop filter was optimized for 40.96 MHz phase detector performance.

Example crystal specifications are presented in Table 117.

Table 117. Example Crystal Specifications

PARAMETER VALUE
Nominal Frequency (MHz) 20.48
Frequency Stability, T = 25 °C ± 10 ppm
Operating temperature range -40 °C to +85 °C
Frequency Stability, -40 °C to +85 °C ± 15 ppm
Load Capacitance 14 pF
Shunt Capacitance (C0) 5 pF Maximum
Motional Capacitance (C1) 20 fF ± 30%
Equivalent Series Resistance 25 Ω Maximum
Drive level 2 mWatts Maximum
C0/C1 ratio 225 typical, 250 Maximum

See Figure 37 for a representative tuning curve.

LMK04208 30102393.gif Figure 37. Example Tuning Curve, 20.48-MHz Crystal

The tuning curve achieved in the user's application may differ from the curve shown above due to differences in PCB layout and component selection.

This data is measured on the bench with the crystal integrated with the LMK04208. Using a voltmeter to monitor the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is valid.

The curve shows over the tuning voltage range of 0.3 VDC to 3.0 VDC, the frequency range is -140 to +91 ppm; or equivalently, a tuning range of -2850 Hz to +1850 Hz. The measured tuning voltage at the nominal crystal frequency (20.48 MHz) is 1.7 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning capacitance of approximately 6.5 pF.

The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal frequency (20.48 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to calculate the ratio:

Equation 13. LMK04208 30102369.gif

ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:

Equation 14. LMK04208 30102335.gif

A second method uses the tuning data in units of ppm:

Equation 15. LMK04208 30102336.gif

FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:

Equation 16. LMK04208 30102337.gif

In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal should conform to the specifications listed in the table of Electrical Characteristics.

It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the crystal, voltage and equivalent series resistance (ESR).

For more complete coverage of crystal oscillator design, see:

Clocks and Timers or AN-1939 Crystal Based Oscillator Design with the LMK04000 Family.

9.2 Typical Applications

Normal use case of the LMK04208 device is as a dual loop jitter cleaner. This section will discuss a design example to illustrate the various functional aspects of the LMK04208 device.

LMK04208 simplified_fbd_dual_loop_mode.gif Figure 38. Simplified Functional Block Diagram for Dual Loop Mode

9.2.1 Design Requirements

Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES, and an LO. The input clock will be a recovered clock which needs jitter cleaning. The FPGA clock should have a clock output on power up. A summary of clock input and output requirements are as follows:

Clock Input:

  • 30.72-MHz recovered clock.

Clock Outputs:

  • 1x 245.76-MHz clock for ADC, LVPECL
  • 2x 983.04-MHz clock for DAC, LVPECL
  • 1x 122.88-MHz clock for FPGA, LVDS. POR clock
  • 1x 122.88-MHz clock for SERDES, LVPECL
  • 2x 122.88-MHz clock for LO, LVCMOS

It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The following information reviews the steps to produce this design.

9.2.2 Detailed Design Procedure

Design of all aspects of the LMK04208 are quite involved and software has been written to assist in part selection, part programming, loop filter design, and simulation. This design procedure will give a quick outline of the process.

Note that this information is current as of the date of the release of this datasheet. Design tools receive continuous improvements to add features and improve model accuracy. Refer to software instructions or training for latest features.

  1. Device Selection
    • the key to device selection is required VCO frequency given required output frequencies. The device must be able to produce the VCO frequency that can be divided down to required output frequencies.
    • The software design tools will take into account VCO frequency range for specific devices based on the application's required output frequencies. Using an external VCO provides increased flexibility regarding valid designs.
    • To understand the process better, refer to Frequency Planning with the LMK04208 for more detail on calculating valid VCO frequency when using integer dividers using the least common multiple (LCM) of the output frequencies.
  2. Device Configuration
    • There are many possible permutations of dividers and other registers to get same input and output frequencies from a device. However there are some optimizations and trade-offs to be considered.
      • If more than one divider is in series, for instance VCO divider to CLKout divider, or VCO divider to PLL prescaler to PLL N. It is possible although not assured that some crosstalk/mixing could be created when using some divides.
    • The design software normally attempts to maximize phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
    • When an external VCXO or crystal is used for jitter cleaning, the design software will choose the maximum frequency value, depending on design software options, this max frequency may be limited to standard value VCXOs/Crystals. Note, depending on application, different frequency VCXOs may be chosen to generate some of the required output frequencies.
    • Refer to PLL Programming for divider equations need to ensure PLL is locked. The design software is able to configure the device for most cases, but at this time for advanced features like 0-delay, the user must take care to ensure proper PLL programming.
    • These guidelines may be followed when configuring PLL related dividers or other related registers:
      • For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
      • For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
      • To reduce loop filter component sizes, increase N value and/or reduce charge pump current.
      • Large capacitors help reduce phase detector spurs at phase detector frequency caused by external VCOs/VCXOs with low input impedance.
      • As rule of thumb, keeping the phase detector frequency approximately between 10 * PLL loop bandwidth and 100 * PLL loop bandwidth. A phase detector frequency less than 5 * PLL bandwidth may be unstable and a phase detector frequency > 100 * loop bandwidth may experience increased lock time due to cycle slipping. However for clock generation/jitter cleaning applications, lock time is typically not critical and large phase detector frequencies typically result in reduced PLL noise, so cycle-slipping during lock is acceptable.
  3. PLL Loop Filter Design
    • TI recommends using Clock Architect to design your loop filter.
    • Best loop filter design and simulation can be achieved when:
      • Custom reference and VCXO phase noise profiles are loaded into the software.
      • VCO gain of the external VCXO or possible external VCO device are entered.
    • The design tool will return solutions with high reference/phase detector frequencies and high charge pump currents by default. It is possible to reduce the phase detector frequency charge pump current in Clock Architect. Due to the narrow loop bandwidth used on PLL1, it is common to lower the phase detector frequency and/or charge pump current on PLL1 to reduce component size.
    • While designing loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but may increase impacts of leakage and reduce PLL phase noise performance.
    • More detailed understanding of loop filter design can found in Dean Banerjee's PLL Performance, Simulation, and Design (www.ti.com/tool/pll_book).
  4. Clock Output Assignment
    • At this time the design software does not take into account frequency assignment to specific outputs except to ensure that the output frequencies can be achieved. It is best to consider proximity of each clock output to each other and other PLL circuitry when choosing final clock output locations. Here are some guidelines to help achieve best performance when assigning outputs to specific CLKout/OSCout pins.
      • Group common frequencies together.
      • PLL charge pump circuitry can cause crosstalk at charge pump frequency. Place outputs sharing charge pump frequency or lower priority outputs not sensitive to charge pump frequency spurs together.
      • Muxes can create a path for noise coupling. Consider all frequencies which may have some bleed through from non-selected mux inputs.
        • For example, LMK04208 CLKout3 and CLKout4 share a mux with OSCin.
    • Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output from CLKout3 or CLKout4 for such a clock target. An example is a clock to a PLL reference.
    • Some clock targets require excellent noise floor performance. Outputs driven by the internal VCO have the best noise floor performance. An example is an ADC or DAC.
  5. Other device specific configuration. For LMK04208, consider the following:
    • PLL lock time based on programming:
      • In addition to the time it takes the device to lock to frequency, there is a digital filter to avoid false lock time detects which can also be used to ensure a specific PPM frequency accuracy. This also impacts the time it takes for the digital lock detect (DLD) pin to be asserted. Refer to Digital Lock Detect Frequency Accuracy for more information.
    • Holdover configuration:
    • Digital delay: phase alignment of the output clocks.
    • Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase noise floor.
    • Dynamic digital delay: ability to shift phase alignment of clocks with minimum disruption during operation.
  6. Device Programming
    • The software tool TICS Pro for EVM programming can be used to setup the device in the desired configuration, then export a hex register map suitable for use in application.

Some additional information on each part of the design procedure for the RRU example is below.

9.2.2.1 Device Selection

Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this device, find a solution using the LMK04208.

9.2.2.1.1 Clock Architect

When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter.

Filtering of a specific device can be done by selecting the device from the filter combo box. Also, regular expressions can be typed into filter combo box. LMK04208 will filter for only the LMK04208 device.

To simulate single loop solutions with dual loop device, set PLL1 loop filter to a very narrow or "0 Hz LBW."

9.2.2.1.2 Calculation Using LCM

In this example, the LCM(245.76 MHz, 983.04 MHz, 122.88 MHz) = 983.04 MHz. A valid VCO frequency for LMK04208 is 2949.12 MHz = 3 * 983.04 MHz. Therefore the LMK04208 may be used to produce these output frequencies.

9.2.2.2 Device Configuration

The tools automatically configure the simulation to meet the input and output frequency requirements given and make assumptions about other parameters to give some default simulations. The assumptions made are to maximize input frequencies, phase detector frequencies, and charge pump currents while minimizing VCO frequency and divider values.

9.2.2.2.1 PLL LO Reference

PLL1 outputs have the best phase noise performance for LO references. As such OSCout, or CLKout3/CLKout4 (with CLKout#_OSCin_Sel field selecting OSCin clock source) can be used to provide the 122.88 MHz LO reference clock. To achieve this with a 245.76 MHz VCXO the OSCout_DIV can be set to 2 to provide 122.88 MHz at OSCout. CLKout3/4_DIV can be set to 2 for 122.88 MHz output if LO references are clocked from CLKout3/4.

In the next section it is determined that for the POR clock, a 122.88 MHz VCXO will be used. This means no division will be needed to provide 122.88 MHz.

9.2.2.2.2 POR Clock

If OSCout is to be used for LVDS POR 122.88 MHz clock, the POR value of the OSCout_DIV is 1, so a 122.88 MHz VCXO frequency must be chosen. This may be desired anyway since the phase detector frequency is limited to 122.88 MHz and lower frequency VCXOs tend to cost less. With this change the OSCin frequency and phase detector frequency are the same, so the doubler must be enabled and the PLL2 R divider programmed = 2 to follow the rule stated in PLL2 Frequency Doubler.

Note: it is possible to set the PLL2 R = 0.5 to simulate the doubler in-case lower frequency VCXOs would like to be simulated. For example a 61.44 MHz VCXO could be used while retaining a 122.88 MHz phase detector frequency. However, it would reduce the LO reference frequency and POR clock frequency to 61.44 MHz.

At this time, the VCXO frequency and phase detector frequency is chosen, so loop filter design may begin.

9.2.2.3 PLL Loop Filter Design

The PLL structure for the LMK04208 is illustrated in Loop Filter.

At this time the user may choose to make adjustments to the simulation tools for more accurate simulations to their application. For example:

  • Clock Architect allows loading a custom phase noise plot for any block. Typically, a custom phase noise plot is entered for CLKin to match the reference phase noise to the device; a phase noise plot for the VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application. After loading a phase noise plot, user should recalculate the recommended loop filter design.
  • The Clock Architect will return solutions with high reference/phase detector frequencies by default. The user may decrease the phase detector frequency if desired. Be sure to decrease by integer relationships with the reference as an integer divider will be used. Due to the narrow loop bandwidth used on PLL1, it is common to reduce the phase detector frequency on PLL1 by increasing PLL1 R.

For this example, for PLL1 to perform jitter cleaning and to minimize jitter from PLL2 used for frequency multiplication:

  • PLL1: A narrow loop bandwidth PLL1 filter was design by updating the loop bandwidth to 50 Hz and phase margin to 50 degrees.
  • PLL2:
    • VCXO noise profile is measured, then loaded into VCXO phase noise profile in Clock Architect. Be sure that the VCO frequency of PLL1 is as desired. If changing the VC(X)O frequency of PLL1, be sure to the PLL2 Phase Detector frequency aligns with an integer divider.
    • The recommended loop filter is redesigned. Updates to the PLL1 loop filter and VCXO phase noise may change the loop filter recommendation, so PLL2 loop filter may need to be recalculated.

The next two sections will discuss PLL1 and PLL2 loop filter design specific to this example using default phase noise profiles.

NOTE

Clock Architect provides some recommend loop filters upon first load of the simulation. Anytime PLL related inputs change like an input phase noise, charge pump current, divider values, and so forth. it is best to re-design the PLL1 loop filter to the recommended design or your desired parameters. After PLL1, then update the PLL2 loop filter in the same way to keep the loop filters designed and optimized for the application. Since PLL1 loop filter design may impact PLL2 loop filter design, be sure to update the designs in order.

9.2.2.3.1 PLL1 Loop Filter Design

For this example, in the Clock Architect tool update the loop bandwidth for 0.05 kHz and the phase margin for 50 degrees and press "Choose RC Components for me." With the 30.72 MHz phase detector frequency and 1.6 mA charge pump; the designed loop filter's largest capacitor, C2, is 27 µF. Supposing a goal of < 10 µF; setting PLL1 R = 4 and pressing the calculate again shows that C2 is 6.8 µF. Suppose that a reduction to < 1 µF is desired, continuing to increase the PLL1 R to 8 resulting in a phase detector frequency of 3.84 MHz and reducing the charge pump current from 1.6 mA to 0.4 mA and calculating again shows that C2 is 820 nF. As N was increased and charge pump decreased, this final design has R2 = 12 kΩ. The first design with low N value and high charge pump current result in R2 = 390 Ω. The impact of the thermal resistance is calculated in the tool. Viewing the simulation of the loop filter with the 12-kΩ resistor shows that the thermal noise in the loop is not impacting performance.

It may be desired to design a 3rd order loop filter for additional attenuation input noise and spurs

With the PLL1 loop filter design complete, PLL2's loop filter is ready to be designed.

9.2.2.3.2 PLL2 Loop Filter Design

In Clock Architect, select LOOPFILTER2 tab under Loop Filters tab. Click "Choose RC Components for me." For PLL2's loop filter maximum phase detector frequency and maximum charge pump current are typically used. Typically the jitter integration bandwidth includes the loop filter bandwidth for PLL2. The recommended loop filter by the tools are designed to minimize jitter. The integrated loop filter components are minimized with this recommendation as to allow maximum flexibility in achieve wide loop bandwidths for low PLL noise. With the recommended loop filter calculated, this loop filter is ready to be simulated.

If using integrated components is desired, make adjustments to the integrated components. The effective loop bandwidth and phase margin with these updates is calculated every time "Update Actual Loop Parameters" is clicked. The integrated loop filter components are good to use when attempting to eliminate some spurs since they provide filtering after the bond wires. The recommended procedure is to increase C3/C4 capacitance, then R3/R4 resistance. Large R3/R4 resistance can result in degraded VCO phase noise performance.

9.2.2.4 Clock Output Assignment

At this time Clock Architect only assign outputs to specific clock outputs numerically; not necessarily by optimum configuration. The user may wish to make some educated re-assignment of outputs.

During device configuration, some output assignment was discussed since it impacted the part's configuration relating to loop filter design, such as:

  • In this example, OSCout can be used to provide the power on reset (POR) start-up clock to the FPGA at 122.88 MHz since the VCXO frequency is the same as the output frequency.
  • Since PLL1 outputs have best in-band noise, CLKout3 is used with CLKout3_OSCin_Sel = 0x01 (OSCin) to provide a PLL1 based output. LVCMOS (Norm/Inv) is used instead of LVCMOS (Norm/Norm) to reduce crosstalk. If OSCout was not needed for FPGA start-up clock, OSCout could have been used to provide the LO reference clocks with lower noise floor, but close-in noise is typically of more concern since noise above the loop bandwidth of the LO will be dominated by the VCO of the LO. See Figure 39.

Since CLKout3 and CLKout4 have a mux allowing them to be driven by the VCXO and due there is a chance for some 122.88 MHz crosstalk from the VCXO. The 122.88 MHz SERDES clock will be placed on CLKout4 since it will not be sensitive to crosstalk as it is operating at the same frequency.

Three converter clocks still need to be assigned. The 245.76 MHz ADC clock and two 983.04 MHz DAC. There are four remaining clock outputs. To maximize distance of the ADC clock from other clocks which could create sub-harmonic spurs, CLKout0 is chosen for ADC at 245.76 MHz clock. CLKout1 and CLKout2 are chosen for the DAC 983.04 MHz clocks. Because the ADC clock is often the most sensitive to sub-harmonic spurs, the goal was to place the ADC clock as far as possible from other clocks which could result in sub-harmonic spurs.

9.2.2.5 Other Device Specific Configuration

9.2.2.5.1 Digital Lock Detect

Digital lock time for PLL1 will ultimately depend upon the programming of the PLL1_DLD_CNT register as discussed in Digital Lock Detect Frequency Accuracy. Since the PLL1 phase detector frequency in this example is 3.84 MHz, the lock time will = 1 / (PLL1_DLD_CNT * 3.84 MHz)

Digital lock time for PLL1 if PLL1_DLD_CNT = 10000 is just over 2.6 ms. When using holdover, it is very important to program the PLL1_DLD_CNT to a value large enough to prevent false digital lock detect signals.

If PLL1_DLD_CNT is too small, when the device exits holdover and is re-locking, the DLD will go high while the phase of the reference and feedback are within the specified window size because the programmed PLL1_DLD_CNT will be satisfied. However, if the loop has not yet settled to without the window size, when the phases of the reference and feedback once again exceed the window size, the DLD will return low. Provided that DISABLE_DLD1_DET = 0, the device once again enter holdover. Assuming that the reference clock is valid because holdover was just exited, the exit criteria will again be met, holdover will exit, and PLL1 will start locking. Unfortunately, the same sequence of events will repeat resulting in oscillation out-of and back-into holdover. Setting the PLL1_DLD_CNT to an appropriately large value prevents chattering of the PLL1 DLD signal and stable holdover operation can be achieved.

Refer to Digital Lock Detect Frequency Accuracy for more detail on calculating exit times and how the PLL1_DLD_CNT and PLL1_WND_SIZE work together.

9.2.2.5.2 Holdover

For this example, when the recovered clock is lost, the goal is to set the VCXO to Vcc/2 until the recovered clock returns. Holdover Mode contains detailed information on how to program holdover.

To achieve the above goal, fixed holdover will be used. Program:

  • HOLDOVER_MODE = 2 (Holdover enabled)
  • EN_TRACK = 0 (Tracking disabled)
  • EN_MAN_DAC = 1 (Use manual DAC for holdover voltage value)
  • MAN_DAC = 512 (Approximately Vcc/2)
  • DISABLE_DLD1_DET = 0 (Use PLL1 DLD = Low to start holdover)

9.2.2.6 Device Programming

The TICS Pro software is used to program the LMK04208 evaluation board using the LMK04208 profile. It also allows the exporting of a register map which can be used to program the device to the user’s desired configuration.

Once a configuration has been achieved using the TICS Pro to meet the requested input/output frequencies with the desired performance, the TICS Pro software is manually updated with this information to meet the required application. At this time no automatic import exists.

9.2.3 Application Curve

LMK04208 D001_SNAS684.gif
Figure 39. LVPECL Phase Noise, 122.88 MHz
Illustration of Different Performance Depending on Signal Path

9.3 System Examples

9.3.1 System Level Diagram

Figure 40 and Figure 41 show an LMK04208 device with external circuitry for clocking and for power supply to serve as a guideline for good practices when designing with the LMK04208. Refer to Pin Connection Recommendations for more details on the pin connections and bypassing recommendations. Also refer to the evaluation board in LMK0480x Evaluation Board Instructions. PCB design will also play a role in device performance. As discussed in PLL LO Reference , the LO clocks at 122.88 MHz may be moved to CLKout5 if the VCXO frequency will support 122.88 MHz output.

LMK04208 Example_Dual_PLL_Application_System_Schematic_except_power.gif Figure 40. Example Application – System Schematic Except for Power

Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-ended. These options are discussed later in the data sheet.

See Loop Filter for more information on PLL1 and PLL2 loop filters.

In the system shown in Figure 40, LVPECL clocks are AC coupled via 0.1 µF capacitors and LVDS clocks are DC coupled. Some clock outputs are depicted as LVPECL with 240-Ω emitter resistors and some clock outputs as LVDS. The appropriate output termination on each output should be implemented according to the output format to be programmed by the user. Later sections of this data sheet illustrate alternative methods for AC coupling, DC coupling, and terminating the clock outputs. PCB design will influence crosstalk performance. Tightly coupled clock traces will have less crosstalk than loosely coupled clock traces. Also proximity to other clocks traces will influence crosstalk.

LMK04208 sch_pwr_internalvco.gif Figure 41. Example Application – Power System Schematic

Figure 41 shows an example decoupling and bypassing scheme for the LMK04208, which could apply to configuration shown in Figure 40. The ferrite beads and capacitors drawn in dotted lines are optional (see Pin Connection Recommendations). Two power planes are used in these example designs, one for the clock outputs and one for PLL circuits. It is possible to reduce the number of decoupling components by tying together clock output Vcc pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between outputs with different frequencies. In the two examples, Vcc2 and Vcc3 can be tied together since CLKout1 and CLKout2 will operate at the same frequencies. Vcc10, Vcc11, and Vcc12 can be tied together since potential crosstalk between the FPGA/SerDes clocks and low-frequency synchronization clocks will not impact the performance of these digital interfaces, which typically have less stringent jitter requirements. PCB design will influence impedance to the supply. Vias and traces will increase the impedance to the power supply. Ensure good direct return current paths.

9.4 Do's and Don'ts

9.4.1 LVCMOS Complementary vs. Non-Complementary Operation

  • TI recommends using a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce switching noise and crosstalk when using LVCMOS.
  • If only a single LVCMOS output is required, the complementary LVCMOS output format can still be used by leaving the unused LVCMOS output floating.
  • A non-complimentary format such as LVCMOS (Norm/Norm) is not recommended as increased switching noise is present.

9.4.2 LVPECL Outputs

When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large switching currents can result in the following:

  1. Large switching currents through the Vcc pin of the LVPECL power supply resulting in more Vcc noise and possible Vcc spikes.
  2. Large switching currents injected into the ground plane through the capacitor which could couple onto other Vcc pins with bypass capacitors to ground resulting in more Vcc noise and possible Vcc spikes.

9.4.3 Sharing MICROWIRE (SPI) Lines

When CLKuWire and DATAuWire toggle and an internal VCO mode is used, there may some spurious content on the phase noise plot related to the frequency of the CLKuWire and DATAuWire pins.