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  • RM57L843 基于 ARM® Cortex®-R 内核的 Hercules™ 微控制器

    • ZHCSF96C February   2014  – June 2016 RM57L843

      PRODUCTION DATA.  

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  • RM57L843 基于 ARM® Cortex®-R 内核的 Hercules™ 微控制器
  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 ZWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 4.2 Terminal Functions
      1. 4.2.1 ZWT Package
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.2.1.3  RAM Trace Port (RTP)
        4. 4.2.1.4  Enhanced Capture Modules (eCAP)
        5. 4.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 4.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 4.2.1.7  Data Modification Module (DMM)
        8. 4.2.1.8  General-Purpose Input / Output (GIO)
        9. 4.2.1.9  Controller Area Network Controllers (DCAN)
        10. 4.2.1.10 Local Interconnect Network Interface Module (LIN)
        11. 4.2.1.11 Standard Serial Communication Interface (SCI)
        12. 4.2.1.12 Inter-Integrated Circuit Interface Module (I2C)
        13. 4.2.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        14. 4.2.1.14 Ethernet Controller
        15. 4.2.1.15 External Memory Interface (EMIF)
        16. 4.2.1.16 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        17. 4.2.1.17 System Module Interface
        18. 4.2.1.18 Clock Inputs and Outputs
        19. 4.2.1.19 Test and Debug Modules Interface
        20. 4.2.1.20 Flash Supply and Test Pads
        21. 4.2.1.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.2.1.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.2.1.23 Ground Reference for All Supplies Except VCCAD
        24. 4.2.1.24 Other Supplies
      2. 4.2.2 Multiplexing
        1. 4.2.2.1 Output Multiplexing
          1. 4.2.2.1.1 Notes on Output Multiplexing
        2. 4.2.2.2 Input Multiplexing
          1. 4.2.2.2.1 Notes on Input Multiplexing
          2. 4.2.2.2.2 General Rules for Multiplexing Control Registers
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required - L2 Memories
    7. 5.7  Power Consumption Summary
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics for the BGA Package (ZWT)
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1 Input Timings
      2. 5.10.2 Output Timings
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R5F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R5F CPU Features
      2. 6.5.2 Dual Core Implementation
      3. 6.5.3 Duplicate Clock Tree After GCLK
      4. 6.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 6.5.4.1 Signal Compare Operating Modes
          1. 6.5.4.1.1 Active Compare Lockstep Mode
          2. 6.5.4.1.2 Self-Test Mode
          3. 6.5.4.1.3 Error Forcing Mode
          4. 6.5.4.1.4 Self-Test Error Forcing Mode
        2. 6.5.4.2 Bus Inactivity Monitor
        3. 6.5.4.3 CPU Registers Initialization
      5. 6.5.5 CPU Self-Test
        1. 6.5.5.1 Application Sequence for CPU Self-Test
        2. 6.5.5.2 CPU Self-Test Clock Configuration
        3. 6.5.5.3 CPU Self-Test Coverage
      6. 6.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 6.6.4 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
        1. 6.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 6.9.5 MasterID to PCRx
      6. 6.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 6.9.7 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings
        1. 6.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 6.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 6.11 L2RAMW (Level 2 RAM Interface Module)
      1. 6.11.1 L2 SRAM Initialization
    12. 6.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Read Timing (Asynchronous RAM)
        2. 6.14.2.2 Write Timing (Asynchronous RAM)
        3. 6.14.2.3 EMIF Asynchronous Memory Timing
        4. 6.14.2.4 Read Timing (Synchronous RAM)
        5. 6.14.2.5 Write Timing (Synchronous RAM)
        6. 6.14.2.6 EMIF Synchronous Memory Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Generation
      3. 6.15.3 Interrupt Request Assignments
    16. 6.16 ECC Error Event Monitoring and Profiling
      1. 6.16.1 EPC Module Operation
        1. 6.16.1.1 Correctable Error Handling
        2. 6.16.1.2 Uncorrectable Error Handling
    17. 6.17 DMA Controller
      1. 6.17.1 DMA Features
      2. 6.17.2 DMA Transfer Port Assignment
      3. 6.17.3 Default DMA Request Map
      4. 6.17.4 Using a GIO terminal as a DMA Request Input
    18. 6.18 Real-Time Interrupt Module
      1. 6.18.1 Features
      2. 6.18.2 Block Diagrams
      3. 6.18.3 Clock Source Options
      4. 6.18.4 Network Time Synchronization Inputs
    19. 6.19 Error Signaling Module
      1. 6.19.1 ESM Features
      2. 6.19.2 ESM Channel Assignments
    20. 6.20 Reset / Abort / Error Sources
    21. 6.21 Digital Windowed Watchdog
    22. 6.22 Debug Subsystem
      1. 6.22.1  Block Diagram
      2. 6.22.2  Debug Components Memory Map
      3. 6.22.3  Embedded Cross Trigger
      4. 6.22.4  JTAG Identification Code
      5. 6.22.5  Debug ROM
      6. 6.22.6  JTAG Scan Interface Timings
      7. 6.22.7  Advanced JTAG Security Module
      8. 6.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 6.22.8.1 ETM TRACECLKIN Selection
        2. 6.22.8.2 Timing Specifications
      9. 6.22.9  RAM Trace Port (RTP)
        1. 6.22.9.1 RTP Features
        2. 6.22.9.2 Timing Specifications
      10. 6.22.10 Data Modification Module (DMM)
        1. 6.22.10.1 DMM Features
        2. 6.22.10.2 Timing Specifications
      11. 6.22.11 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time-Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connection to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.4.1 MibADC Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MibADC1 Event Trigger Hookup
        2. 7.4.2.2 MibADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Interconnections
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI2 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI3 Event Trigger Hookup
        4. 7.11.3.4 MIBSPI4 Event Trigger Hookup
        5. 7.11.3.5 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Timing
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Design or Reference Design
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device and Development-Support Tool Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation from Texas Instruments
      2. 9.2.2 Receiving Notification of Documentation Updates
      3. 9.2.3 社区资源
    3. 9.3 商标
    4. 9.4 静电放电警告
    5. 9.5 Glossary
    6. 9.6 Device Identification
      1. 9.6.1 Device Identification Code Register
      2. 9.6.2 Die Identification Registers
    7. 9.7 Module Certifications
      1. 9.7.1 DCAN Certification
      2. 9.7.2 LIN Certification
        1. 9.7.2.1 LIN Master Mode
        2. 9.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Data
    1. 10.1 Packaging Information
  11. 重要声明
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DATA SHEET

RM57L843 基于 ARM® Cortex®-R 内核的 Hercules™ 微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 高性能微控制器，适用于安全关键型 应用
    • 双核锁步 CPU，具有 ECC 保护缓存
    • 闪存和 RAM 接口上的 ECC
    • 针对 CPU、高端定时器和片上 RAM 的内置自检
    • 带有错误引脚的错误信令模块 (ESM)
    • 电压和时钟监视
  • ARM®Cortex®- R5F 32 位 RISC CPU
    • 单精度和双精度 FPU
    • 16 区域存储器保护单元 (MPU)
    • 配有 32KB 的指令和 32KB 的数据缓存（支持 ECC）
    • 带有第三方支持的开放式架构
  • 运行条件
    • 高达 MHzMHzMHz330MHz 的 CPU 时钟
    • 内核电源电压(VCC)：1.14V 至 1.32V
    • I/O 电源电压 (VCCIO)：3.0V 至 3.6V
  • 集成存储器
    • 支持 ECC 的 4MB 程序闪存
    • KB512KBKB 的 RAM（支持 ECC）
    • 用于仿真的 EERPOM 的 128KB 数据闪存（支持 ECC）
  • 16 位外部存储器接口 (EMIF)
  • Hercules™通用平台架构
    • 系列间一致的存储器映射
    • 实时中断 (RTI) 定时器（操作系统 (OS) 定时器）
    • 2 个具有向量表 ECC 保护的 128 通道向量中断模块 (VIM)
      • VIM1 和 VIM2 运行在安全锁步模式下
    • 2 个双通道循环冗余校验器 (CRC) 模块
  • 直接存储器访问 (DMA) 控制器
    • 32 个通道和 48 个外设请求
    • 针对控制包 RAM 的 ECC 保护
    • 由专用 MPU 保护的 DMA 访问
  • 内置跳周检测器的调频锁相环 (FMPLL)
  • 独立的非调制 PLL
  • IEEE 1149.1 JTAG，边界扫描和 ARM CoreSight™组件
  • 高级 JTAG 安全模块 (AJSM) 
  • 跟踪和校准功能
    • ETM™、RTP、DMM、POM
  • 多通信接口
    • 10/100Mbps 以太网 MAC (EMAC)
      • IEEE 802.3 兼容（只适用于 3.3V I/O）
      • 支持 MII、RMII 和 MDIO
    • 四个 CAN 控制器 (DCAN) 模块
      • 64 个支持 ECC 保护的邮箱
      • 与 CAN 协议 2.0B 版兼容
    • 2 个内部集成电路 (I2C) 模块
    • 五个多通道缓冲串行外设接口 (MibSPI) 模块
      • MibSPI1：256 个字，支持 ECC 保护
      • 其他 MibSPI：128 个字，支持 ECC 保护
    • 4 个通用异步收发器 (UART) (SCI) 接口，其中 2 个支持本地互连网络 (LIN 2.1)
  • 2 个新一代高端定时器 (N2HET) 模块
    • 每个模块拥有 32 个可编程通道
    • 带有奇偶校验的 256 字指令 RAM
    • 每个 N2HET 都带有硬件角度生成器
    • 每个 N2HET 都带有专用高端定时器传输单元 (HTU)
  • 2 个 12 位多通道缓冲模数转换器 (MibADC) 模块
    • MibADC1：32 通道 + 针对高达 1024 个片外通道的控制
    • MibADC2：25 通道
    • 16 个共享通道
    • 64 个具有奇偶校验保护的结果缓冲器
  • 增强型定时外设
    • 7 个增强型脉宽调制器 (ePWM) 模块
    • 6 个增强型捕捉 (eCAP) 模块
    • 2 个增强型正交编码器脉冲 (eQEP) 模块
  • 3 个片上温度传感器
  • 多达 145 个通用 I/O (GPIO) 引脚
  • 16 个具有外部中断功能的专用 GPIO 引脚
  • 封装
    • 337 焊球栅格阵列 (ZWT) 封装 [绿色环保]

1.2 应用

  • 工业安全 应用范围
    • 工业自动化
    • 工业电机驱动
    • 安全可编程逻辑控制器 (PLC)
    • 发电和配电
    • 涡轮机和风力发动机
    • 电梯和自动扶梯

1.3 说明

RM57L843 器件属于 Hercules RM 系列的高性能基于 ARM® Cortex®-R 的 MCU。该器件配有完备的文档、工具和软件，可协助开发 IEC 61508 功能安全 应用。目前，首先使用 Hercules RM57x LaunchPad 开发套件进行评估。RM57L843 器件具有片上诊断 特性 ，具体包括：锁步中的双 CPU；针对 CPU、N2HET 协处理器以及片上 SRAM 的内置自检 (BIST) 逻辑；L1 缓存、L2 闪存和 SRAM 存储器上的 ECC 保护。此外，该器件还为外设存储器提供了 ECC 或奇偶校验保护，外设 I/O 上具有环回功能。

RM57L843 器件集成有 2 个锁步运行的 ARM Cortex-R5F 浮点 CPU，效率高达 1.66 DMIPS/MHz，经过高达 MHzMHzMHz330MHz 下运行，从而提供高达 DMIPSDMIPS547DMIPSDMIPSDMIPS 的性能。器件支持 小尾数法 [LE] 格式。

RM57L843 器件具有支持单位纠错和双位错误检测功能的 4MB 的集成闪存和 512KB 的数据 RAM 。该器件上的闪存存储器是实现了 64 位宽数据总线接口的可电擦除且可编程的非易失性存储器。对于所有读取、编程和擦除操作，该闪存都工作在 3.3V 电源输入（与 I/O 电源相同的电平）。SRAM 支持字节、半字和字模式的读取/写入访问。

RM57L843 器件 具有 针对实时控制类 应用的外设，包括 2 个 I/O 引脚总数高达 64 的新一代高端定时器 (N2HET) 时序协处理器。

N2HET 是一款高级智能定时器，能够为实时应用提供精密的计时 功能。该定时器为软件控制型，并具有一个专用的定时器微级机和一个连接的 I/O 端口。N2HET 可用于脉宽调制输出、捕捉或比较输入，或 GPIO。N2HET 特别适用于 那些 需要多个传感器信息或者用复杂和准确时间脉冲来驱动致动器的应用。高端定时器传输单元 (HTU) 能够执行 DMA 类型事务来与主存储器之间传输 N2HET 数据。HTU 中内置有存储器保护单元 (MPU)。

增强型脉宽调制器 (ePWM) 模块能够依赖极少的 CPU 开销或干预生成复杂的脉宽波形。ePWM 易于使用，并且支持高侧和低侧 PWM 以及死区生成。ePWM集成有触发区保护并且与片上 MibADC 同步，因此非常适合数字电机控制 应用。

如果系统注重外部事件的准时捕捉，那么增强型捕捉 (eCAP) 模块将是必不可少的。eCAP 还能够用于监控 ePWM 输出，或者在应用无需捕捉时轻松生成 PWM。

增强型正交编码器脉冲 (eQEP) 模块直接连接一个线性或旋转递增编码器，进而从一个高性能运动和位置控制系统中正在旋转的机械中获得位置、方向、和速度信息。

该器件具有 2 个 12 位分辨率 MibADC，共有 41 个通道以及带奇偶校验保护的 64 字缓冲 RAM。MibADC 通道可被独立转换或者可针对特殊转换序列由软件分组转换。16 个通道可在两个 MibADC 间共用。每个 MibADC 均支持 3 个独立的分组。每个序列可在被触发时转换一次，或者通过配置以执行连续转换模式。MibADC 具有一个 10 位模式，可兼容早期器件，并且可在需要提高转换速率时使用。MibADC1 中的一个通道和 MibADC2 中的两个通道可搭配用于转换来自 3 个片上温度传感器的温度测量值。

该器件具有多个通信接口：5 个 MibSPI；4 个 UART (SCI) 接口、其中 2 个支持 LIN； 4 个 CAN； 2 个 I2C 模块；以及 1 个以太网控制器。SPI 为相似的移位寄存器类型器件之间的高速通信提供了一种便捷的串行交互方法。LIN 支持本地互联标准 (LIN 2.1) 并可被用作一个使用标准不归零码 (NRZ) 格式的全双工模式 UART。DCAN 支持 CAN 2.0B 协议标准并使用串行多主机通信协议，此协议有效支持对最高速率为 1Mbps 的稳健通信实现分布式实时控制。DCAN 非常适用于 那些 嘈杂和恶劣环境中的应用（例如：汽车和工业领域），此类应用需要可靠的串行通信或多路复用布线。 以太网模块支持 MII、RMII 和管理数据 I/O (MDIO) 接口。 I2C 模块是一个多主机通信模块，可为微控制器和与 I2C 兼容的器件之间提供接口（通过 I2C 串行总线）。I2C 模块支持 100kbps 和 400kbps 的速率。

调频锁相环 (FMPLL) 时钟模块会将外部频率基准与一个内部使用的更高频率相乘。全局时钟模块 (GCM) 管理可用时钟源与内部器件时钟域间的映射。

该器件还具有 2 个外部时钟预分频器 (ECP) 模块。ECP 使能时，会在 ECLK1 和 ECLK2 焊球上输出一个连续的外部时钟。ECLK 频率是一个外设接口时钟 (VCLK) 频率的用户可编程比例。这个可被外部监视的低频输出作为此器件运行频率的指示器。

直接存储器访问 (DMA) 控制器具有 32 个通道、48 个外设请求以及对其存储器的 ECC 保护。DMA 内置有 MPU，用于保护存储器免遭错误传输。

错误信令模块 (ESM) 监控片上器件错误并在检测到故障时确定是触发一个中断还是触发一个外部错误引脚/焊球 (nERROR)。可从外部监视 nERROR 信号，作为微控制器内故障条件的指示器。

外部存储器接口 (EMIF) 提供对异步和同步存储器或者其他从器件的存储器扩展。

该器件包含参数覆盖模块，可增强应用代码的调试功能。POM 可将到内部 RAM 或到 EMIF 的闪存访问重新路由，从而避免针对闪存中的参数更新进行重新编程。该功能在实时系统校准过程中特别有用。

该器件实现了若干个接口，可增强应用代码的调试功能。除了内置的 ARM Cortex-R5F CoreSight 调试 特性，还有嵌入式交叉触发器 (ECT) 支持 SoC 内多个触发事件的交互和同步。外部跟踪宏单元 (ETM) 提供程序执行的指令和数据跟踪。为了实现仪器测量的目的，执行了一个 RAM 跟踪端口模块 (RTP) 来支持由 CPU 或者任何其它主控所访问的 RAM 和外设的高速跟踪。 一个数据修改模块 (DMM) 提供向器件内存写入外部数据的功能。RTP 和 DMM 对应用代码的程序执行时间影响非常小。

凭借集成的安全 特性 以及各类通信和控制外设，RM57L843 器件非常适合对安全要求严格 的 高性能实时控制应用。

Table 1-1 器件信息(1)

器件编号 封装 封装尺寸
RM57L843ZWT NFBGA (337) 16.00mm x 16.00mm
(1) 有关这些器件的更多信息，请参见Section 9，机械、封装和可订购信息。

1.4 功能方框图

Figure 1-1可展示器件的功能框图

RM57L843 lockstep_catalog_RM_bd2.gif Figure 1-1 功能方框图

2 修订历史记录

本数据手册修订历史记录强调了将 SPNS215B 器件专用数据手册变为 SPNS215C 修订版本所做的技术更改。这些器件现处于开发的量产数据 (PD) 阶段。

Changes from January 31, 2016 to June 25, 2016 (from B Revision (January 2016) to C Revision)

  • 全局：将产品状态从“产品预览”更新/更改为“量产数据”。Go
  • Section 1.2 (应用程序）：已更新/更改的部分Go
  • Table 6-13 (LPO Specifications): Updated/Changed LPO - HF oscillator, Untrimmed frequency TYP value from "9.6" to "9" MHzGo
  • Section 6.9.3 (Special Consideration for CPU Access Errors Resulting in Imprecise Aborts): Add missing subsectionGo
  • Added 300MHz limit to PBIST testing of ATB RAM Go
  • Section 6.14.1 (External Memory Interface (EMIF), Features): Updated/Changed the EMIF asynchronous memory maximum addressable size from "32KB" to "16MB" eachGo
  • Section 6.14 (External Memory Interface (EMIF)): Added 32-bit access note using a 16-bit EMIF interface.Go
  • Added "Commonly caused by ..." statement for clarificationGo
  • Table 6-56 (ETMTRACECLK Timing): Restructured timing table formatting to standardsGo
  • Table 7-7, (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in the MODULE INSTANCE columnGo
  • Table 7-11, (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in the MODULE INSTANCE columnGo
  • Table 7-16 (MibADC1 Event Trigger Selection): Added lead-in paragraph referencing the ableGo
  • (MibADC1 Event Trigger Hookup): NOTE: Added new paragraphGo
  • Table 7-17 (MibADC2 Event Trigger Selection): Added lead-in paragraph referencing the ableGo
  • Section 7.4.2.3 (Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules): Updated/Changed the names of the four ePWM signals that event trigger the ADCGo
  • Table 7-22 (MibADC Operating Characteristics Over 3.0 V to 3.6 V Operating Conditions): Updated/Changed the 10- and 12-bit mode formulas to be superscript power of 2 valuesGo
  • Table 7-23 (MibADC Operating Characteristics Over 3.6 V to 5.25 V Operating Conditions): Updated/Changed the 10- and 12-bit mode formulas to be superscript power of 2 valuesGo
  • Figure 9-1 (RM57L843 Device Numbering Conventions): Updated/Changed imageGo

3 Device Comparison

Table 3-1 lists the features of the RM57L843 devices.

Table 3-1 RM57L843 Device Comparison(2)(3)

FEATURES DEVICES
Generic Part Number RM57L843ZWT(1) RM48L952ZWT(1) RM48L950PGE RM48L750PGE RM48L550ZWT RM48L550PGE RM46L852ZWT(1)
Package 337 BGA 337 BGA 144 QFP 144 QFP 337 BGA 144 QFP 337 BGA
CPU ARM Cortex-R5F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
Frequency (MHz) 330 220 200 200 200 200 220
Cache (KB) 32 I
32 D		 – – – – – –
Flash (KB) 4096 3072 3072 2048 2048 2048 1280
RAM (KB) 512 256 256 256 192 192 192
Data Flash [EEPROM] (KB) 128 64 64 64 64 64 64
USB OHCI + Device – 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1
EMAC 10/100 10/100 10/100 10/100 10/100 10/100 10/100
CAN 4 3 3 3 3 3 3
MibADC 12-bit (Ch) 2 (41ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch)
N2HET (Ch) 2 (64) 2 (44) 2 (40) 2 (40) 2 (44) 2 (40) 2 (44)
ePWM Channels 14 – – – – – 14
eCAP Channels 6 – – – – – 6
eQEP Channels 2 – – – – – 2
MibSPI (CS) 5 (4 x 6 + 2) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4)
SPI (CS) – 2 (2 + 1) 1 (1) 1 (1) 2 (2 + 1) 1 (1) 2 (2 + 1)
SCI (LIN) 4 (2 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN)
I2C 2 1 1 1 1 1 1
GPIO (INT)(4) 168 (with 16 interrupt capable) 144 (with 16 interrupt capable) 64 (with 4 interrupt capable) 64 (with 4 interrupt capable) 144 (with 16 interrupt capable) 64 (with 4 interrupt capable) 101 (with 16 interrupt capable)
EMIF 16-bit data 16-bit data – – 16-bit data – 16-bit data
ETM [Trace] (Data) (32) (32) – – 32-bit – –
RTP/DMM (Data) (16/16) (16/16) – – 16/16 – –
Operating Temperature –40ºC to 105ºC –40ºC to 105ºC –40ºC to 105ºC –40ºC to 105ºC –40ºC to 105ºC –40ºC to 105ºC –40ºC to 105ºC
Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V
I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V
(1) Superset device
(2) For additional device variants, see www.ti.com/rm
(3) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time.
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral

4 Terminal Configuration and Functions

4.1 ZWT BGA Package Ball-Map (337 Terminal Grid Array)

RM57L843 337ZWT_automotive_ball_map_RM57_f5.gif Figure 4-1 ZWT Package Pinout. Top View

Note: Balls can have multiplexed functions. See Section 4.2.2 for detailed information.

4.2 Terminal Functions

Table 4-1 through Table 4-26 identify the external signal names, the associated terminal numbers along with the mechanical package designator, the terminal type (Input, Output, I/O, Power, or Ground), whether the terminal has any internal pullup/pulldown, whether the terminal can be configured as a GIO, and a functional terminal description. The first signal name listed is the primary function for that terminal. The signal name in Bold is the function being described. For information on how to select between different multiplexed functions, see the Section 4.2.2, Multiplexing of this data manual along with the I/O Multiplexing Module (IOMM) chapter in the Technical Reference Manual (TRM) ( SPNU562).

NOTE

In the Terminal Functions tables below, the "Default Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.


All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.


All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.

4.2.1 ZWT Package

4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADC)

Table 4-1 ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

TERMINAL SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER
DRIVE STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1 N19 I/O Pulldown Programmable, 20 µA 2mA ZD ADC1 event trigger input, or GIO
AD1IN[0] W14 Input - - - ADC1 Input
AD1IN[1] V17 Input - - - ADC1 Input
AD1IN[2] V18 Input - - - ADC1 Input
AD1IN[3] T17 Input - - - ADC1 Input
AD1IN[4] U18 Input - - - ADC1 Input
AD1IN[5] R17 Input - - - ADC1 Input
AD1IN[6] T19 Input - - - ADC1 Input
AD1IN[7] V14 Input - - - ADC1 Input
AD1IN[8]/AD2IN[8] P18 Input - - - ADC1/ADC2 shared Input
AD1IN[9]/AD2IN[9] W17 Input - - - ADC1/ADC2 shared Input
AD1IN[10]/AD2IN[10] U17 Input - - - ADC1/ADC2 shared Input
AD1IN[11]/AD2IN[11] U19 Input - - - ADC1/ADC2 shared Input
AD1IN[12]/AD2IN[12] T16 Input - - - ADC1/ADC2 shared Input
AD1IN[13]/AD2IN[13] T18 Input - - - ADC1/ADC2 shared Input
AD1IN[14]/AD2IN[14] R18 Input - - - ADC1/ADC2 shared Input
AD1IN[15]/AD2IN[15] P19 Input - - - ADC1/ADC2 shared Input
AD1IN[16]/AD2IN[0] V13 Input - - - ADC1/ADC2 shared Input
AD1IN[17]/AD2IN[1] U13 Input - - - ADC1/ADC2 shared Input
AD1IN[18]/AD2IN[2] U14 Input - - - ADC1/ADC2 shared Input
AD1IN[19]/AD2IN[3] U16 Input - - - ADC1/ADC2 shared Input
AD1IN[20]/AD2IN[4] U15 Input - - - ADC1/ADC2 shared Input
AD1IN[21]/AD2IN[5] T15 Input - - - ADC1/ADC2 shared Input
AD1IN[22]/AD2IN[6] R19 Input - - - ADC1/ADC2 shared Input
AD1IN[23]/AD2IN[7] R16 Input - - - ADC1/ADC2 shared Input
AD1IN[24] N18 Input - - - ADC1 Input
AD1IN[25] P17 Input - - - ADC1 Input
AD1IN[26] P16 Input - - - ADC1 Input
AD1IN[27] P15 Input - - - ADC1 Input
AD1IN[28] R15 Input - - - ADC1 Input
AD1IN[29] R14 Input - - - ADC1 Input
AD1IN[30] T14 Input - - - ADC1 Input
AD1IN[31] T13 Input - - - ADC1 Input(1)
AD2EVT T10 I/O Pulldown Programmable, 20 µA 2mA ZD ADC2 event trigger input, or GIO
MIBSPI3NCS[0]/AD2EVT/eQEP1I V10(2)
AD2IN[16] W13 Input - - - ADC2 Input
AD2IN[17] W12 Input - - - ADC2 Input
AD2IN[18] V12 Input - - - ADC2 Input
AD2IN[19] U12 Input - - - ADC2 Input
AD2IN[20] T11 Input - - - ADC2 Input
AD2IN[21] U11 Input - - - ADC2 Input
AD2IN[22] V11 Input - - - ADC2 Input
AD2IN[23] W11 Input - - - ADC2 Input
AD2IN[24] V19 Input - - - ADC2 Input
AD2IN[24] W18
ADREFHI V15(3) Input - - - ADC high reference supply
ADREFLO V16(3) Input - - - ADC low reference supply
MIBSPI3SOMI/AD1EXT_ENA/ECAP2 V8 Output Pullup 20 µA 2mA ZD External Mux ENA
MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA G16
MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3 W8 Output Pullup 20 µA 2mA ZD External Mux Select 0
MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0] E16
MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A V9 Output Pullup 20 µA 2mA ZD External Mux Select 1
MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1] H17
MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2] G17 Output Pullup 20 µA 2mA ZD External Mux Select 2
MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3] E17 Output Pullup 20 µA 2mA ZD External Mux Select 3
MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4] H16 Output Pullup 20 µA 2mA ZD External Mux Select 4
VCCAD W15(3) Input - - - Operating supply for ADC
VSSAD W16(3) Input - - - ADC supply ground
VSSAD W19(3) Input - - - ADC supply ground
  1. This ADC channel is also multiplexed with an internal temperature sensor.
  2. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.
  3. The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.

4.2.1.2 Enhanced High-End Timer Modules (N2HET)

Table 4-2 ZWT Enhanced High-End Timer Modules (N2HET)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
N2HET1[0]/MIBSPI4CLK/ePWM2B K18 I/O Pulldown Programmable, 20 µA 2 mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A V2 I/O Pulldown Programmable, 20 µA 2 mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[2]/MIBSPI4SIMO/ePWM3A W5 I/O Pulldown Programmable, 20 µA 2 mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B U1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[4]/MIBSPI4NCS[1]/ePWM4B B12 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B V6 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[6]/SCI3RX/ePWM5A W3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B T1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 I/O Pulldown Programmable, 20 µA 8mA N2HET1 time input capture or output compare, or GIO
N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A V7 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3 D19 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO E3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV B4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B N2 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[14] A11 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1 N1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO A4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[17]/EMIF_nOE/SCI4RX A13 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S F3(1)
N2HET1[18]/EMIF_RNW/ePWM6A J1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[19]/EMIF_nDQM[0]/SCI4TX B13 I/O Pulldown Programmable, 20 µA 2m A ZD N2HET1 time input capture or output compare, or GIO
MIBSPI1NCS[2]/MDIO/N2HET1[19] G3(1)
N2HET1[20]/EMIF_nDQM[1]/ePWM6B P2 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[21]/EMIF_nDQM[2] H4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3 J3(1)
N2HET1[22]/EMIF_nDQM[3] B3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[23]/EMIF_BA[0] J4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4 G19(1)
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[25] M3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI3NCS[1]/MDCLK/N2HET1[25] V5(1)
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[27] A9 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2 B2(1)
N2HET1[28]/MII_RXCLK/RMII_REFCLK K19 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[29] A3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1 C3(1)
N2HET1[30]/MII_RX_DV/eQEP2S B11 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
N2HET1[31] J17 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET1 time input capture or output compare, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9(1)
N2HET2[0] D6 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
GIOA[2]/N2HET2[0]/eQEP2I C1(1)
N2HET2[1]/N2HET1_NDIS D8 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_ADDR[0]/N2HET2[1] D4(1)
N2HET2[2]/N2HET2_NDIS D7 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
GIOA[3]/N2HET2[2] E1(1)
N2HET2[3]/MIBSPI2CLK E2 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_ADDR[1]/N2HET2[3] D5(1)
N2HET2[4] D13 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
GIOA[6]/N2HET2[4]/ePWM1B H3(1)
N2HET2[5] D12 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_BA[1]/N2HET2[5] D16(1)
N2HET2[6] D11 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
GIOA[7]/N2HET2[6]/ePWM2A M1(1)
N2HET2[7]/MIBSPI2NCS[0] N3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17(1)
N2HET2[8] K16 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A V2(1)
N2HET2[9] L16 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17(1)
N2HET2[10] M16 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B U1(1)
N2HET2[11] N16 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4(1)
N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1] D3 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B V6(1)
N2HET2[13]/MIBSPI2SOMI D2 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5(1)
N2HET2[14]/MIBSPI2SIMO D1 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B T1(1)
N2HET2[15] K4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6(1)
N2HET2[16] L4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A V7(1)
N2HET2[17] M4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET2[18] N4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO E3(1)
N2HET2[19]/LIN2RX P4 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET2[20]/LIN2TX T5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B N2(1)
N2HET2[21] T6 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET2[22] T7 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1 N1(1)
N2HET2[23] T8 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4] L5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5] M5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[26]/EMIF_DATA[10]/N2HET2[26] N5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[27]/EMIF_DATA[11]/N2HET2[27] P5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0] R5 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1] R6 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3] R7 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4] R8 I/O Pulldown Programmable, 20 µA 2mA ZD N2HET2 time input capture or output compare, or GIO
N2HET2[1]/N2HET1_NDIS D8 Input Pulldown Fixed, 20 µA 2mA ZD N2HET1 Disable
N2HET2[2]/N2HET2_NDIS D7 Input Pulldown Fixed, 20 µA 2mA ZD N2HET2 Disable
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.3 RAM Trace Port (RTP)

Table 4-3 ZWT RAM Trace Port (RTP)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
EMIF_ADDR[21]/RTP_CLK C17 I/O Pulldown Programmable, 20 µA 8mA RTP packet clock, or GIO
EMIF_ADDR[18]/RTP_DATA[0] D15 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[17]/RTP_DATA[1] C14 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[16]/RTP_DATA[2] D14 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[15]/RTP_DATA[3] C13 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[14]/RTP_DATA[4] C12 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[13]/RTP_DATA[5] C11 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[12]/RTP_DATA[6] C10 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_nCS[4]/RTP_DATA[7]/GIOB[5] M17 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[11]/RTP_DATA[8] C9 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[10]/RTP_DATA[9] C8 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[9]/RTP_DATA[10] C7 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 I/O Pulldown Programmable, 20 µA 8mA RTP packet data, or GIO
EMIF_ADDR[19]/RTP_nENA C15 I/O Pullup Programmable, 20 µA 8mA RTP packet handshake, or GIO
EMIF_ADDR[20]/RTP_nSYNC C16 I/O Pullup Programmable, 20 µA 8mA RTP synchronization, or GIO
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.4 Enhanced Capture Modules (eCAP)

Table 4-4 ZWT Enhanced Capture Modules (eCAP)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1 N1 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 1 I/O
MIBSPI3SOMI/AD1EXT_ENA/ECAP2 V8 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 2 I/O
MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3 W8 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 3 I/O
MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4 G19 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 4 I/O
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5 H18 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Pullup Fixed, 20 µA 8mA Enhanced Capture Module 6 I/O

4.2.1.5 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-5 ZWT Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A V9 Input Pullup Fixed, 20 µA - Enhanced QEP1 Input A
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9 Input Pullup Fixed, 20 µA - Enhanced QEP1 Input B
MIBSPI3NCS[0]/AD2EVT/eQEP1I V10 I/O Pullup Fixed, 20 µA 8mA Enhanced QEP1 Index
MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S F3 I/O Pullup Fixed, 20 µA 8mA Enhanced QEP1 Strobe
N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A V2 Input Pullup Fixed, 20 µA - Enhanced QEP2 Input A
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B U1 Input Pullup Fixed, 20 µA - Enhanced QEP2 Input B
GIOA[2]/N2HET2[0]/eQEP2I C1 I/O Pullup Fixed, 20 µA 8mA Enhanced QEP2 Index
N2HET1[30]/MII_RX_DV/eQEP2S B11 I/O Pullup Fixed, 20 µA 8mA Enhanced QEP2 Strobe
  1. These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.6 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-6 ZWT Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL SIGNAL
TYPE		 DEFAULT
PULL
STATE		 PULL
TYPE		 OUTPUT
BUFFER
DRIVE
STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
ePWM1A D9 Output – – 8 mA Enhanced PWM1 Output A
GIOA[5]/EXTCLKIN1/ePWM1A B5(1)
ePWM1B D10 Output – – 8 mA Enhanced PWM1 Output B
GIOA[6]/N2HET2[4]/ePWM1B H3(1)
N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO A4 Input Pulldown Fixed, 20 µA – External ePWM Sync Pulse Input
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/
ePWM1SYNCO 		E3 Output Pulldown 20 µA 2mA ZD External ePWM Sync Pulse Output
N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO A4(1)
GIOA[7]/N2HET2[6]/ePWM2A M1 Output Pulldown 20 µA 8 mA Enhanced PWM2 Output A
N2HET1[0]/MIBSPI4CLK/ePWM2B K18 Output Pulldown 20 µA 8 mA Enhanced PWM2 Output B
N2HET1[2]/MIBSPI4SIMO/ePWM3A W5 Output Pulldown 20 µA 8 mA Enhanced PWM3 Output A
N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B V6 Output Pulldown 20 µA 8 mA Enhanced PWM3 Output B
MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A E19 Output Pulldown 20 µA 8 mA Enhanced PWM4 Output A
N2HET1[4]/MIBSPI4NCS[1]/ePWM4B B12 Output Pulldown 20 µA 8 mA Enhanced PWM4 Output B
N2HET1[6]/SCI3RX/ePWM5A W3 Output Pulldown 20 µA 8 mA Enhanced PWM5 Output A
N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B N2 Output Pulldown 20 µA 8 mA Enhanced PWM5 Output B
N2HET1[18]/EMIF_RNW/ePWM6A J1 Output – – 8 mA Enhanced PWM6 Output A
N2HET1[20]/EMIF_nDQM[1]/ePWM6B P2 Output – – 8 mA Enhanced PWM6 Output B
N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A V7 Output – – 8 mA Enhanced PWM7 Output A
N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B T1 Output – – 8 mA Enhanced PWM7 Output B
AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1 N19 Input Pulldown Fixed, 20 µA – Trip Zone 1 Input 1
MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1 C3(1)
GIOB[7]/nTZ1_2 F1 Input Pulldown Fixed, 20 µA – Trip Zone 1 Input 2
MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2 B2(1)
MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3 J3 Input Pullup Fixed, 20 µA – Trip Zone 1 Input 3
N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3 D19(1)
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.7 Data Modification Module (DMM)

Table 4-7 ZWT Data Modification Module (DMM)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
DMM_CLK F17 I/O Pullup Programmable, 20 µA 2mA ZD DMM clock, or GIO
DMM_DATA[0] L19 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
DMM_DATA[1] L18 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5NCS[2]/DMM_DATA[2] W6 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5NCS[3]/DMM_DATA[3] T12 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A E19 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5NCS[1]/DMM_DATA[6] B6 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5 H18 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0] E16 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1] H17 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2] G17 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3] E17 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4] H16 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA G16 I/O Pullup Programmable, 20 µA 2mA ZD DMM data, or GIO
DMM_nENA F16 I/O Pullup Programmable, 20 µA 2mA ZD DMM handshake, or GIO
DMM_SYNC J16 I/O Pullup Programmable, 20 µA 2mA ZD DMM synchronization, or GIO

4.2.1.8 General-Purpose Input / Output (GIO)

Table 4-8 ZWT General-Purpose Input / Output (GIO)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
GIOA[0] A5 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0] R5(1)
GIOA[1] C2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1] R6(1)
GIOA[2]/N2HET2[0]/eQEP2I C1 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
GIOA[3]/N2HET2[2] E1 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3] R7(1)
GIOA[4] A6 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4] R8(1)
GIOA[5]/EXTCLKIN1/ePWM1A B5 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMTRACECLKIN/EXTCLKIN2/GIOA[5] R9(1)
GIOA[6]/N2HET2[4]/ePWM1B H3 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMTRACECLKOUT/GIOA[6] R10(1)
GIOA[7]/N2HET2[6]/ePWM2A M1 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
ETMTRACECTL/GIOA[7] R11(1)
GIOB[0] M2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
GIOB[1] K2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
GIOB[2]/DCAN4TX F2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
GIOB[3]/DCAN4RX W10 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
EMIF_nCAS/GIOB[3] R4(1)
GIOB[4] G1 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
EMIF_nCS[2]/GIOB[4] L17(1)
GIOB[5] G2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
EMIF_nCS[4]/RTP_DATA[7]/GIOB[5] M17(1)
GIOB[6]/nERROR J2 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
EMIF_nRAS/GIOB[6] R3(1)
GIOB[7]/nTZ1_2 F1 I/O Pulldown Programmable, 20 µA 2mA ZD General-purpose I/O, external interrupt capable
EMIF_nWAIT/GIOB[7] P3(1)
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.9 Controller Area Network Controllers (DCAN)

Table 4-9 ZWT Controller Area Network Controllers (DCAN)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
DCAN1RX B10 I/O Pullup Programmable, 20 µA 2mA ZD CAN1 receive, or GIO
DCAN1TX A10 I/O Pullup Programmable, 20 µA 2mA ZD CAN1 transmit, or GIO
DCAN2RX H1 I/O Pullup Programmable, 20 µA 2mA ZD CAN2 receive, or GIO
DCAN2TX H2 I/O Pullup Programmable, 20 µA 2mA ZD CAN2 transmit, or GIO
DCAN3RX M19 I/O Pullup Programmable, 20 µA 2mA ZD CAN3 receive, or GIO
DCAN3TX M18 I/O Pullup Programmable, 20 µA 2mA ZD CAN3 transmit, or GIO
GIOB[3]/DCAN4RX W10 I/O Pulldown Programmable, 20 µA 2mA ZD CAN4 receive, or GIO
GIOB[2]/DCAN4TX F2 I/O Pulldown Programmable, 20 µA 2mA ZD CAN4 transmit, or GIO

4.2.1.10 Local Interconnect Network Interface Module (LIN)

Table 4-10 ZWT Local Interconnect Network Interface Module (LIN)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
LIN1RX A7 I/O Pullup Programmable, 20 µA 2mA ZD LIN receive, or GIO
LIN1TX B7 I/O Pullup Programmable, 20 µA 2mA ZD LIN transmit, or GIO
N2HET2[19]/LIN2RX P4 I/O Pulldown Programmable, 20 µA 2mA ZD LIN receive, or GIO
N2HET2[20]/LIN2TX T5 I/O Pulldown Programmable, 20 µA 2mA ZD LIN transmit, or GIO

4.2.1.11 Standard Serial Communication Interface (SCI)

Table 4-11 ZWT Standard Serial Communication Interface (SCI)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
N2HET1[6]/SCI3RX/ePWM5A W3 I/O Pulldown Programmable, 20 µA 2mA ZD SCI receive, or GIO
N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B N2 I/O Pulldown Programmable, 20 µA 2mA ZD SCI transmit, or GIO
N2HET1[17]/EMIF_nOE/SCI4RX A13 I/O Pulldown Programmable, 20 µA 2mA ZD SCI receive, or GIO
N2HET1[19]/EMIF_nDQM[0]/SCI4TX B13 I/O Pulldown Programmable, 20 µA 2mA ZD SCI transmit, or GIO

4.2.1.12 Inter-Integrated Circuit Interface Module (I2C)

Table 4-12 ZWT Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1 C3 I/O Pullup Programmable, 20 µA 2mA ZD I2C serial clock, or GIO
MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2 B2 I/O Pullup Programmable, 20uA 2mA ZD I2C serial data, or GIO
MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA G16 I/O Pullup Programmable, 20uA 2mA ZD I2C serial clock, or GIO
MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2] G17 I/O Pullup Programmable, 20uA 2mA ZD I2C serial data, or GIO

4.2.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-13 ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
MIBSPI1CLK F18 I/O Pullup Programmable, 20 µA 8mA MibSPI1 clock, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Pullup Programmable, 20 >µA 8mA MibSPI1 chip select, or GIO
MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S F3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[2]/MDIO /N2HET1[19] G3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3 J3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[4] U10 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1 N1(1)
MIBSPI1NCS[5] U9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1(1)
MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4 G19 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 enable, or GIO
MIBSPI1SIMO[0] F19 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-in master-out, or GIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 I/O Pulldown Programmable, 20 µA 8mA MibSPI1 slave-in master-out, or GIO
MIBSPI1SOMI[0] G18 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-out master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-out master-in, or GIO
N2HET2[3]/MIBSPI2CLK E2 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 clock, or GIO
N2HET2[7]/MIBSPI2NCS[0] N3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 chip select, or GIO
N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1] D3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 chip select, or GIO
N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1] D3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 enable, or GIO
N2HET2[14]/MIBSPI2SIMO D1 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 slave-in master-out, or GIO
N2HET2[13]/MIBSPI2SOMI D2 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 slave-out master-in, or GIO
MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A V9 I/O Pullup Programmable, 20 µA 8mA MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/eQEP1I V10 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[1]/MDCLK/N2HET1[25] V5 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27] /nTZ1_2 B2 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29] /nTZ1_1 C3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO E3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 enable, or GIO
MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3 W8 I/O Pullup Programmable, 20 µA 8mA MibSPI3 slave-in master-out, or GIO
MIBSPI3SOMI/AD1EXT_ENA/ECAP2 V8 I/O Pullup Programmable, 20 µA 8mA MibSPI3 slave-out master-in, or GIO
N2HET1[0]/MIBSPI4CLK/ePWM2B K18 I/O Pulldown Programmable, 20 µA 8mA MibSPI4 clock, or GIO
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B U1 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO
N2HET1[4]/MIBSPI4NCS[1]/ePWM4B B12 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO
N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B T1 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO
N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A V7 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO
N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3 D19 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV B4 I/O Pulldown Programmable, 20 µA 4mA MibSPI4 chip select, or GIO
N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A V2 I/O Pulldown Programmable, 20 µA 8mA MibSPI4 enable, or GIO
N2HET1[2]/MIBSPI4SIMO/ePWM3A W5 I/O Pulldown Programmable, 20 µA 8mA MibSPI4 slave-in master-out, or GIO
N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B V6 I/O Pulldown Programmable, 20 µA 8mA MibSPI4 slave-out master-in, or GIO
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 I/O Pullup Programmable, 20 µA 8mA MibSPI5 clock, or GIO
MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A E19 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
MIBSPI5NCS[1]/DMM_DATA[6] B6 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
MIBSPI5NCS[2]/DMM_DATA[2] W6 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
MIBSPI5NCS[3]/DMM_DATA[3] T12 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4] L5 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5] M5 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 chip select, or GIO
MIBSPI5NENA/DMM_DATA[7] /MII_RXD[3]/ECAP5 H18 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI5 enable, or GIO
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-in master-out, or GIO
MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0] E16 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-in master-out, or GIO
MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1] H17 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-in master-out, or GIO
MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2] G17 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-in master-out, or GIO
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-out master-in, or GIO
MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3] E17 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-out master-in, or GIO
MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4] H16 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-out master-in, or GIO
MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA G16 I/O Pullup Programmable, 20 µA 8mA MibSPI5 slave-out master-in, or GIO
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.14 Ethernet Controller

Table 4-14 ZWT Ethernet Controller: MDIO Interface

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
MDCLK T9 Output - - 8mA Serial clock output
MIBSPI3NCS[1]/MDCLK/N2HET1[25] V5(1)
MDIO F4 I/O Pulldown Fixed, 20 µA 8mA Serial data input/output
MIBSPI1NCS[2]/MDIO/N2HET1[19] G3(1)
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

Table 4-15 ZWT Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV B4 Input Pulldown Fixed, 20 µA - RMII carrier sense and data valid
N2HET1[28]/MII_RXCLK/RMII_REFCLK K19 Input Pulldown Fixed, 20 µA 8mA EMII synchronous reference clock for receive, transmit and control interface
AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1 N19 Input Pulldown Fixed, 20 µA - RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 Input Pulldown Fixed, 20 µA - RMII receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 Input Pulldown Fixed, 20 µA - RMII receive data
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 Output Pullup 20 µA 8mA RMII transmit data
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 Output Pullup 20 µA 8mA RMII transmit data
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 Output Pullup 20 µA 8mA RMII transmit enable

Table 4-16 ZWT Ethernet Controller: Media Independent Interface (MII)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
MII_COL W4 Input Pullup Fixed, 20 µA - Collision detect
MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S F3(1)
MII_CRS V4 Input Pulldown Fixed, 20 µA - Carrier sense and receive valid
N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV B4(1)
MII_RX_DV U6 Input Pulldown Fixed, 20 µA - Received data valid
N2HET1[30]/MII_RX_DV/eQEP2S B11(1)
MII_RX_ER U5 Input Pulldown Fixed, 20 µA - Receive error
AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1 N19(1)
MII_RXCLK T4 Input Pulldown Fixed, 20 µA - Receive clock
N2HET1[28]/MII_RXCLK/RMII_REFCLK K19(1)
MII_RXD[0] U4 Input Pulldown Fixed, 20 µA - Receive data
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1(1)
MII_RXD[1] T3 Input Pulldown Fixed, 20 µA - Receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14(1)
MII_RXD[2] U3 Input Pulldown Fixed, 20 µA - Receive data
MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4 G19(1)
MII_RXD[3] V3 Input Pulldown Fixed, 20 µA - Receive data
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5 H18(1)
MII_TX_CLK U7 Input Pulldown Fixed, 20 µA - Transmit clock
N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3 D19(1)
MII_TXD[0] U8 Output - - 8mA Transmit data
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18(1)
MII_TXD[1] R1 Output - - 8mA Transmit data
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19(1)
MII_TXD[2] T2 Output - - 8mA Transmit data
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2(1)
MII_TXD[3] G4 Output - - 8mA Transmit data
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18(1)
MII_TXEN E4 Output - - 8mA Transmit enable
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19(1)
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.

4.2.1.15 External Memory Interface (EMIF)

Table 4-17 External Memory Interface (EMIF)(2)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
EMIF_ADDR[0]/N2HET2[1] D4 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[1]/N2HET2[3] D5 Output Pulldown 20 µA 8mA EMIF address
ETMDATA[11]/EMIF_ADDR[2] E6 Output - - 8mA EMIF address
ETMDATA[10]/EMIF_ADDR[3] E7 Output - - 8mA EMIF address
ETMDATA[9]/EMIF_ADDR[4] E8 Output - - 8mA EMIF address
ETMDATA[8]/EMIF_ADDR[5] E9 Output - - 8mA EMIF address
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[9]/RTP_DATA[10] C7 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[10]/RTP_DATA[9] C8 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[11]/RTP_DATA[8] C9 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[12]/RTP_DATA[6] C10 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[13]/RTP_DATA[5] C11 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[14]/RTP_DATA[4] C12 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[15]/RTP_DATA[3] C13 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[16]/RTP_DATA[2] D14 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[17]/RTP_DATA[1] C14 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[18]/RTP_DATA[0] D15 Output Pulldown 20 µA 8mA EMIF address
EMIF_ADDR[19]/RTP_nENA C15 Output Pullup 20 µA 8mA EMIF address
EMIF_ADDR[20]/RTP_nSYNC C16 Output Pullup 20 µA 8mA EMIF address
EMIF_ADDR[21]/RTP_CLK C17 Output Pulldown 20 µA 8mA EMIF address
ETMDATA[12]/EMIF_BA[0] E13 Output Pulldown 20 µA 8mA EMIF bank address or address line
N2HET1[23]/EMIF_BA[0] J4(1)
EMIF_BA[1]/N2HET2[5] D16 Output Pulldown 20 µA 8mA EMIF bank address or address line
EMIF_CKE L3 Output - - 8mA EMIF clock enable
EMIF_CLK/ECLK2 K3 Output Pulldown 20 µA 8mA EMIF clock
ETMDATA[16]/EMIF_DATA[0] K15 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[17]/EMIF_DATA[1] L15 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[18]/EMIF_DATA[2] M15 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[19]/EMIF_DATA[3] N15 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[20]/EMIF_DATA[4] E5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[21]/EMIF_DATA[5] F5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[22]/EMIF_DATA[6] G5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[23]/EMIF_DATA[7] K5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4] L5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5] M5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[26]/EMIF_DATA[10]/N2HET2[26] N5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[27]/EMIF_DATA[11]/N2HET2[27] P5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0] R5 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1] R6 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3] R7 I/O Pulldown Fixed, 20 µA 8mA EMIF data
ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4] R8 I/O Pulldown Fixed, 20 µA 8mA EMIF data
EMIF_nCAS/GIOB[3] R4 Output Pulldown 20 µA 8mA EMIF column address strobe
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 Output Pulldown 20 µA 8mA EMIF chip select, synchronous
EMIF_nCS[2]/GIOB[4] L17 Output Pulldown 20 µA 8mA EMIF chip select, asynchronous
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Output Pulldown 20 µA 8mA EMIF chip select, asynchronous
EMIF_nCS[4]/RTP_DATA[7]/GIOB[5] M17 Output Pulldown 20 µA 8mA EMIF chip select, asynchronous
ETMDATA[15]/EMIF_nDQM[0] E10 Output Pulldown 20 µA 8mA EMIF byte enable
N2HET1[19]/EMIF_nDQM[0]/SCI4TX B13(1)
ETMDATA[14]/EMIF_nDQM[1] E11 Output Pulldown 20 µA 8mA EMIF byte enable
N2HET1[20]/EMIF_nDQM[1]/ePWM6B P2(1)
N2HET1[21]/EMIF_nDQM[2] H4 Output Pulldown 20 µA 8mA EMIF byte enable
N2HET1[22]/EMIF_nDQM[3] B3 Output Pulldown 20 µA 8mA EMIF byte enable
ETMDATA[13]/EMIF_nOE E12 Output Pulldown 20 µA 8mA EMIF output enable
N2HET1[17]/EMIF_nOE/SCI4RX A13(1)
EMIF_nRAS/GIOB[6] R3 Output Pulldown 20 µA 8mA EMIF row address strobe
EMIF_nWAIT/GIOB[7] P3 Input Pullup Fixed, 20 µA - EMIF wait
EMIF_nWE/EMIF_RNW D17 Output - - 8mA EMIF write enable
EMIF_nWE/EMIF_RNW D17 Output - - 8mA EMIF read-not-write
N2HET1[18]/EMIF_RNW/ePWM6A J1(1)
  1. This is the secondary terminal at which the signal is also available. See Section 4.2.2.2 for more detail on how to select between the available terminals for input functionality.
  2. By default, the EMIF interface pins are the primary pins before configurating the IOMM (IO Muxing Module). The output buffers of these pins are forced to tri-state until enabled by setting PINMMR174[8] = 0 and PINMMR174[9] = 1.”

4.2.1.16 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)

Table 4-18 ZWT Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
ETMDATA[0] R12 Output Pulldown 20 µA 8mA ETM data
ETMDATA[1] R13 Output Pulldown 20 µA 8mA ETM data
ETMDATA[2] J15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[3] H15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[4] G15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[5] F15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[6] E15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[7] E14 Output Pulldown 20 µA 8mA ETM data
ETMDATA[8]/EMIF_ADDR[5] E9 Output Pulldown 20 µA 8mA ETM data
ETMDATA[9]/EMIF_ADDR[4] E8 Output Pulldown 20 µA 8mA ETM data
ETMDATA[10]/EMIF_ADDR[3] E7 Output Pulldown 20 µA 8mA ETM data
ETMDATA[11]/EMIF_ADDR[2] E6 Output Pulldown 20 µA 8mA ETM data
ETMDATA[12]/EMIF_BA[0] E13 Output Pulldown 20 µA 8mA ETM data
ETMDATA[13]/EMIF_nOE E12 Output Pulldown 20 µA 8mA ETM data
ETMDATA[14]/EMIF_nDQM[1] E11 Output Pulldown 20 µA 8mA ETM data
ETMDATA[15]/EMIF_nDQM[0] E10 Output Pulldown 20 µA 8mA ETM data
ETMDATA[16]/EMIF_DATA[0] K15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[17]/EMIF_DATA[1] L15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[18]/EMIF_DATA[2] M15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[19]/EMIF_DATA[3] N15 Output Pulldown 20 µA 8mA ETM data
ETMDATA[20]/EMIF_DATA[4] E5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[21]/EMIF_DATA[5] F5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[22]/EMIF_DATA[6] G5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[23]/EMIF_DATA[7] K5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4] L5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5] M5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[26]/EMIF_DATA[10]/N2HET2[26] N5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[27]/EMIF_DATA[11]/N2HET2[27] P5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0] R5 Output Pulldown 20 µA 8mA ETM data
ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1] R6 Output Pulldown 20 µA 8mA ETM data
ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3] R7 Output Pulldown 20 µA 8mA ETM data
ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4] R8 Output Pulldown 20 µA 8mA ETM data
ETMTRACECLKIN/EXTCLKIN2/GIOA[5] R9 Input Pullup Fixed, 20 µA - ETM trace clock input
ETMTRACECLKOUT/GIOA[6] R10 Output Pulldown 20 µA 8mA ETM trace clock output
ETMTRACECTL/GIOA[7] R11 Output Pulldown 20 µA 8mA ETM trace control

4.2.1.17 System Module Interface

Table 4-19 ZWT System Module Interface

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
nERROR B14 Output Pulldown 20 µA 8mA ESM error (And of Error 1 and Error 2)
GIOB[6]/nERROR J2 Output Pulldown 20 µA 8mA ESM error 1
nPORRST W7 Input Pulldown 100 µA - Power-on reset, cold reset
nRST B17 I/O Pullup 100 µA 4mA System reset, warm reset

4.2.1.18 Clock Inputs and Outputs

Table 4-20 ZWT Clock Inputs and Outputs

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
ECLK1 A12 I/O Pulldown Programmable, 20 µA 2mA ZD/8mA External clock output, or GIO
EMIF_CLK/ECLK2 K3 I/O Pulldown Programmable, 20 µA 2mA ZD/8mA External clock output, or GIO
GIOA[5]/EXTCLKIN1/ePWM1A B5 Input Pulldown Fixed, 20 µA - External clock input
ETMTRACECLKIN/EXTCLKIN2/GIOA[5] R9 Input Pullup Fixed, 20 µA - External clock input # 2
KELVIN_GND L2 Input - - - Kelvin ground for oscillator
OSCIN K1 Input - - - From external crystal/resonator, or external clock input
OSCOUT L1 Output - - - To external crystal/resonator

4.2.1.19 Test and Debug Modules Interface

Table 4-21 ZWT Test and Debug Modules Interface

TERMINAL SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER
DRIVE STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
nTRST D18 Input Pulldown 100 µA - JTAG test hardware reset
TCK B18 Input Pulldown Fixed, 100 µA - JTAG test clock
TDI A17 Input Pullup Fixed, 100 µA - JTAG test data in
TDO C18 Output Pulldown Fixed, 100 µA 8mA JTAG test data out
TEST U2 Input Pulldown Fixed, 100 µA - Test mode enable. This terminal must be connected to ground directly or through a pulldown resistor.
TMS C19 Input Pullup Fixed, 100 µA - JTAG test mode select
RTCK A16 Output - - 8mA JTAG return test clock

4.2.1.20 Flash Supply and Test Pads

Table 4-22 ZWT Flash Supply and Test Pads

TERMINAL SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER
DRIVE STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
VCCP F8 3.3-V Power – – – Flash pump supply
FLTP1 J5 Input – – – Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 H5 Input – – –

4.2.1.21 Supply for Core Logic: 1.2-V Nominal

Table 4-23 ZWT Supply for Core Logic: 1.2-V Nominal

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
VCC P10 1.2-V Power - - - Core supply
VCC L6 - - - Core supply
VCC K6 - - - Core supply
VCC F9 - - - Core supply
VCC F10 - - - Core supply
VCC J14 - - - Core supply
VCC K14 - - - Core supply
VCC M10 - - - Core supply
VCC K8 - - - Core supply
VCC H10 - - - Core supply
VCC K12 - - - Core supply

4.2.1.22 Supply for I/O Cells: 3.3-V Nominal

Table 4-24 ZWT Supply for I/O Cells: 3.3-V Nominal

Terminal Signal Type Default Pull State Pull Type Output Buffer
Drive Strength		 Description
Signal Name 337 ZWT
VCCIO F11 3.3-V Power – – – Operating supply for I/Os
VCCIO F12 – – – Operating supply for I/Os
VCCIO F13 – – – Operating supply for I/Os
VCCIO F14 – – – Operating supply for I/Os
VCCIO G14 – – – Operating supply for I/Os
VCCIO H14 – – – Operating supply for I/Os
VCCIO L14 – – – Operating supply for I/Os
VCCIO M14 – – – Operating supply for I/Os
VCCIO N14 – – – Operating supply for I/Os
VCCIO P14 – – – Operating supply for I/Os
VCCIO P13 – – – Operating supply for I/Os
VCCIO P12 – – – Operating supply for I/Os
VCCIO P9 – – – Operating supply for I/Os
VCCIO P8 – – – Operating supply for I/Os
VCCIO P7 – – – Operating supply for I/Os
VCCIO P6 – – – Operating supply for I/Os
VCCIO N6 – – – Operating supply for I/Os
VCCIO M6 – – – Operating supply for I/Os
VCCIO J6 – – – Operating supply for I/Os
VCCIO H6 – – – Operating supply for I/Os
VCCIO G6 – – – Operating supply for I/Os
VCCIO F6 – – – Operating supply for I/Os
VCCIO F7 – – – Operating supply for I/Os

4.2.1.23 Ground Reference for All Supplies Except VCCAD

Table 4-25 ZWT Ground Reference for All Supplies Except VCCAD

TERMINAL SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER
DRIVE STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
VSS W1 Ground – – – Ground reference
VSS V1 – – – Ground reference
VSS W2 – – – Ground reference
VSS B1 – – – Ground reference
VSS A1 – – – Ground reference
VSS A2 – – – Ground reference
VSS A18 – – – Ground reference
VSS A19 – – – Ground reference
VSS B19 – – – Ground reference
VSS M8 – – – Ground reference
VSS M9 – – – Ground reference
VSS M11 – – – Ground reference
VSS M12 – – – Ground reference
VSS L8 – – – Ground reference
VSS L9 – – – Ground reference
VSS L10 – – – Ground reference
VSS L11 – – – Ground reference
VSS L12 – – – Ground reference
VSS K9 – – – Ground reference
VSS K10 – – – Ground reference
VSS K11 – – – Ground reference
VSS J8 – – – Ground reference
VSS J9 – – – Ground reference
VSS J10 – – – Ground reference
VSS J11 – – – Ground reference
VSS J12 – – – Ground reference
VSS H8 – – – Ground reference
VSS H9 – – – Ground reference
VSS H11 – – – Ground reference
VSS H12 – – – Ground reference

4.2.1.24 Other Supplies

Table 4-26 Other Supplies

TERMINAL SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER
DRIVE STRENGTH		 DESCRIPTION
SIGNAL NAME 337 ZWT
Supply for PLL: 1.2-V nominal
VCCPLL P11 1.2-V Power – – – Core supply for PLL's

4.2.2 Multiplexing

This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from an alternative terminal. For more information on multiplexing, refer to the IOMM chapter of the device specific technical reference manual.

4.2.2.1 Output Multiplexing

Table 4-27 Output Multiplexing

Address
Offset		 337
ZWT
BALL		 DEFAULT FUNCTION Select
Bit		 Alternate Function 1 Select
Bit		 Alternate Function 2 Select
Bit		 Alternate Function 3 Select
Bit		 Alternate Function 4 Select
Bit		 Alternate Function 5 Select
Bit
0x110 N19 AD1EVT 0[0] MII_RX_ER 0[2] RMII_RX_ER 0[3] nTZ1_1 0[5]
D4 EMIF_ADDR[0] 0[8] N2HET2[1] 0[10]
D5 EMIF_ADDR[1] 0[16] N2HET2[3] 0[18]
C4 EMIF_ADDR[6] 0[24] RTP_DATA[13] 0[25] N2HET2[11] 0[26]
0x114 C5 EMIF_ADDR[7] 1[0] RTP_DATA[12] 1[1] N2HET2[13] 1[2]
C6 EMIF_ADDR[8] 1[8] RTP_DATA[11] 1[9] N2HET2[15] 1[10]
C7 EMIF_ADDR[9] 1[16] RTP_DATA[10] 1[17]
C8 EMIF_ADDR[10] 1[24] RTP_DATA[9] 1[25]
0x118 C9 EMIF_ADDR[11] 2[0] RTP_DATA[8] 2[1]
C10 EMIF_ADDR[12] 2[8] RTP_DATA[6] 2[9]
C11 EMIF_ADDR[13] 2[16] RTP_DATA[5] 2[17]
C12 EMIF_ADDR[14] 2[24] RTP_DATA[4] 2[25]
0x11C C13 EMIF_ADDR[15] 3[0] RTP_DATA[3] 3[1]
D14 EMIF_ADDR[16] 3[8] RTP_DATA[2] 3[9]
C14 EMIF_ADDR[17] 3[16] RTP_DATA[1] 3[17]
D15 EMIF_ADDR[18] 3[24] RTP_DATA[0] 3[25]
0x120 C15 EMIF_ADDR[19] 4[0] RTP_nENA 4[1]
C16 EMIF_ADDR[20] 4[8] RTP_nSYNC 4[9]
C17 EMIF_ADDR[21] 4[16] RTP_CLK 4[17]
0x124
-
0x12C		 Reserved
0x130 PINMMR8[23:0] are reserved
D16 EMIF_BA[1] 8[24] 8[25] N2HET2[5] 8[26]
0x134 K3 RESERVED 9[0] EMIF_CLK 9[1] ECLK2 9[2]
R4 EMIF_nCAS 9[8] GIOB[3] 9[10]
N17 EMIF_nCS[0] 9[16] RTP_DATA[15] 9[17] N2HET2[7] 9[18]
L17 EMIF_nCS[2] 9[24] GIOB[4] 9[26]
0x138 K17 EMIF_nCS[3] 10[0] RTP_DATA[14] 10[1] N2HET2[9] 10[2]
M17 EMIF_nCSl[4] 10[8] RTP_DATA[7] 10[9] GIOB[5] 10[10]
R3 EMIF_nRAS 10[16] GIOB[6] 10[18]
P3 EMIF_nWAIT 10[24] GIOB[7] 10[26]
0x13C D17 EMIF_nWE 11[0] EMIF_RNW 11[1]
E9 ETMDATA[8] 11[8] EMIF_ADDR[5] 11[9]
E8 ETMDATA[9] 11[16] EMIF_ADDR[4] 11[17]
E7 ETMDATA[10] 11[24] EMIF_ADDR[3] 11[25]
0x140 E6 ETMDATA[11] 12[0] EMIF_ADDR[2] 12[1]
E13 ETMDATA[12] 12[8] EMIF_BA[0] 12[9]
E12 ETMDATA[13] 12[16] EMIF_nOE 12[17]
E11 ETMDATA[14] 12[24] EMIF_nDQM[1] 12[25]
0x144 E10 ETMDATA[15] 13[0] EMIF_nDQM[0] 13[1]
K15 ETMDATA[16] 13[8] EMIF_DATA[0] 13[9]
L15 ETMDATA[17] 13[16] EMIF_DATA[1] 13[17]
M15 ETMDATA[18] 13[24] EMIF_DATA[2] 13[25]
0x148 N15 ETMDATA[19] 14[0] EMIF_DATA[3] 14[1]
E5 ETMDATA[20] 14[8] EMIF_DATA[4] 14[9]
F5 ETMDATA[21] 14[16] EMIF_DATA[5] 14[17]
G5 ETMDATA[22] 14[24] EMIF_DATA[6] 14[25]
0x14C K5 ETMDATA[23] 15[0] EMIF_DATA[7] 15[1]
L5 ETMDATA[24] 15[8] EMIF_DATA[8] 15[9] N2HET2[24] 15[10] MIBSPI5NCS[4] 15[11]
M5 ETMDATA[25] 15[16] EMIF_DATA[9] 15[17] N2HET2[25] 15[18] MIBSPI5NCS[5] 15[19]
N5 ETMDATA[26] 15[24] EMIF_DATA[10] 15[25] N2HET2[26] 15[26]
0x150 P5 ETMDATA[27] 16[0] EMIF_DATA[11] 16[1] N2HET2[27] 16[2]
R5 ETMDATA[28] 16[8] EMIF_DATA[12] 16[9] N2HET2[28] 16[10] GIOA[0] 16[11]
R6 ETMDATA[29] 16[16] EMIF_DATA[13] 16[17] N2HET2[29] 16[18] GIOA[1] 16[19]
R7 ETMDATA[30] 16[24] EMIF_DATA[14] 16[25] N2HET2[30] 16[26] GIOA[3] 16[27]
0x154 R8 ETMDATA[31] 17[0] EMIF_DATA[15] 17[1] N2HET2[31] 17[2] GIOA[4] 17[3]
R9 ETMTRACECLKIN 17[8] EXTCLKIN2 17[9] GIOA[5] 17[11]
R10 ETMTRACECLKOUT 17[16] GIOA[6] 17[19]
R11 ETMTRACECTL 17[24] GIOA[7] 17[27]
0x15C C1 GIOA[2] 19[0] N2HET2[0] 19[2] eQEP2I 19[5]
E1 GIOA[3] 19[8] N2HET2[2] 19[10]
B5 GIOA[5] 19[16] EXTCLKIN1 19[19] ePWM1A 19[21]
H3 GIOA[6] 19[24] N2HET2[4] 19[26] ePWM1B 19[29]
0x160 M1 GIOA[7] 20[0] N2HET2[6] 20[2] ePWM2A 20[5]
F2 GIOB[2] 20[8] DCAN4TX 20[11]
W10 GIOB[3] 20[16] DCAN4RX 20[19]
J2 GIOB[6] 20[24] nERROR 20[25]
0x164 F1 GIOB[7] 21[0] RESERVED 21[1] nTZ1_2 21[5]
R2 MIBSPI1NCS[0] 21[8] MIBSPI1SOMI[1] 21[9] MII_TXD[2] 21[10] ECAP6 21[13]
F3 MIBSPI1NCS[1] 21[16] MII_COL 21[18] N2HET1[17] 21[19] eQEP1S 21[21]
G3 MIBSPI1NCS[2] 21[24] MDIO 21[26] N2HET1[19] 21[27]
0x168 J3 MIBSPI1NCS[3] 22[0] N2HET1[21] 22[3] nTZ1_3 22[5]
G19 MIBSPI1NENA 22[8] MII_RXD[2] 22[10] N2HET1[23] 22[11] ECAP4 22[13]
V9 MIBSPI3CLK 22[16] AD1EXT_SEL[1] 22[17] eQEP1A 22[21]
V10 MIBSPI3NCS[0] 22[24] AD2EVT 22[25] eQEP1I 22[29]
0x16C V5 MIBSPI3NCS[1] 23[0] MDCLK 23[2] N2HET1[25] 23[3]
B2 MIBSPI3NCS[2] 23[8] I2C1_SDA 23[9] N2HET1[27] 23[11] nTZ1_2 23[13]
C3 MIBSPI3NCS[3] 23[16] I2C1_SCL 23[17] N2HET1[29] 23[19] nTZ1_1 23[21]
W9 MIBSPI3NENA 23[24] MIBSPI3NCS[5] 23[25] N2HET1[31] 23[27] eQEP1B 23[29]
0x170 W8 MIBSPI3SIMO 24[0] AD1EXT_SEL[0] 24[1] ECAP3 24[5]
V8 MIBSPI3SOMI 24[8] AD1EXT_ENA 24[9] ECAP2 24[13]
H19 MIBSPI5CLK 24[16] DMM_DATA[4] 24[17] MII_TXEN 24[18] RMII_TXEN 24[19]
E19 MIBSPI5NCS[0] 24[24] DMM_DATA[5] 24[25] ePWM4A 24[29]
0x174 B6 MIBSPI5NCS[1] 25[0] DMM_DATA[6] 25[1]
W6 MIBSPI5NCS[2] 25[8] DMM_DATA[2] 25[9]
T12 MIBSPI5NCS[3] 25[16] DMM_DATA[3] 25[17]
H18 MIBSPI5NENA 25[24] DMM_DATA[7] 25[25] MII_RXD[3] 25[26] ECAP5 25[29]
0x178 J19 MIBSPI5SIMO[0] 26[0] DMM_DATA[8] 26[1] MII_TXD[1] 26[2] RMII_TXD[1] 26[3]
E16 MIBSPI5SIMO[1] 26[8] DMM_DATA[9] 26[9] AD1EXT_SEL[0] 26[12]
H17 MIBSPI5SIMO[2] 26[16] DMM_DATA[10] 26[17] AD1EXT_SEL[1] 26[20]
G17 MIBSPI5SIMO[3] 26[24] DMM_DATA[11] 26[25] I2C2_SDA 26[26] AD1EXT_SEL[2] 26[28]
0x17C J18 MIBSPI5SOMI[0] 27[0] DMM_DATA[12] 27[1] MII_TXD[0] 27[2] RMII_TXD[0] 27[3]
E17 MIBSPI5SOMI[1] 27[8] DMM_DATA[13] 27[9] AD1EXT_SEL[3] 27[12]
H16 MIBSPI5SOMI[2] 27[16] DMM_DATA[14] 27[17] AD1EXT_SEL[4] 27[20]
G16 MIBSPI5SOMI[3] 27[24] DMM_DATA[15] 27[25] I2C2_SCL 27[26] AD1EXT_ENA 27[28]
0x180 K18 N2HET1[0] 28[0] MIBSPI4CLK 28[1] ePWM2B 28[5]
V2 N2HET1[1] 28[8] MIBSPI4NENA 28[9] N2HET2[8] 28[11] eQEP2A 28[13]
W5 N2HET1[2] 28[16] MIBSPI4SIMO 28[17] ePWM3A 28[21]
U1 N2HET1[3] 28[24] MIBSPI4NCS[0] 28[25] N2HET2[10] 28[27] eQEP2B 28[29]
0x184 B12 N2HET1[4] 29[0] MIBSPI4NCS[1] 29[1] ePWM4B 29[5]
V6 N2HET1[5] 29[8] MIBSPI4SOMI 29[9] N2HET2[12] 29[11] ePWM3B 29[13]
W3 N2HET1[6] 29[16] SCI3RX 29[17] ePWM5A 29[21]
T1 N2HET1[7] 29[24] MIBSPI4NCS[2] 29[25] N2HET2[14] 29[27] ePWM7B 29[29]
0x188 E18 N2HET1[8] 30[0] MIBSPI1SIMO[1] 30[1] MII_TXD[3] 30[2]
V7 N2HET1[9] 30[8] MIBSPI4NCS[3] 30[9] N2HET2[16] 30[11] ePWM7A 30[13]
D19 N2HET1[10] 30[16] MIBSPI4NCS[4] 30[17] MII_TX_CLK 30[18] RESERVED 30[19] nTZ1_3 30[21]
E3 N2HET1[11] 30[24] MIBSPI3NCS[4] 30[25] N2HET2[18] 30[27] ePWM1SYNCO 30[29]
0x18C B4 N2HET1[12] 31[0] MIBSPI4NCS[5] 31[1] MII_CRS 31[2] RMII_CRS_DV 31[3]
N2 N2HET1[13] 31[8] SCI3TX 31[9] N2HET2[20] 31[11] ePWM5B 31[13]
N1 N2HET1[15] 31[16] MIBSPI1NCS[4] 31[17] N2HET2[22] 31[19] ECAP1 31[21]
A4 N2HET1[16] 31[24] ePWM1SYNCI 31[27] ePWM1SYNCO 31[29]
0x190 A13 N2HET1[17] 32[0] EMIF_nOE 32[1] SCI4RX 32[2]
J1 N2HET1[18] 32[8] EMIF_RNW 32[9] ePWM6A 32[13]
B13 N2HET1[19] 32[16] EMIF_nDQM[0] 32[17] SCI4TX 32[18]
P2 N2HET1[20] 32[24] EMIF_nDQM[1] 32[25] ePWM6B 32[29]
0x194 H4 N2HET1[21] 33[0] EMIF_nDQM[2] 33[1]
B3 N2HET1[22] 33[8] EMIF_nDQM[3] 33[9]
J4 N2HET1[23] 33[16] EMIF_BA[0] 33[17]
P1 N2HET1[24] 33[24] MIBSPI1NCS[5] 33[25] MII_RXD[0] 33[26] RMII_RXD[0] 33[27]
0x198 A14 N2HET1[26] 34[0] MII_RXD[1] 34[2] RMII_RXD[1] 34[3]
K19 N2HET1[28] 34[8] MII_RXCLK 34[10] RMII_REFCLK 34[11] RESERVED 34[12]
B11 N2HET1[30] 34[16] MII_RX_DV 34[18] eQEP2S 34[21]
D8 N2HET2[1] 34[24] N2HET1_NDIS 34[25]
0x19C D7 N2HET2[2] 35[0] N2HET2_NDIS 35[1]
D3 N2HET2[12] 35[8] MIBSPI2NENA 35[12] MIBSPI2NCS[1] 35[13]
D2 N2HET2[13] 35[16] MIBSPI2SOMI 35[20]
D1 N2HET2[14] 35[24] MIBSPI2SIMO 35[28]
0x1A0 P4 N2HET2[19] 36[0] LIN2RX 36[1]
T5 N2HET2[20] 36[8] LIN2TX 36[9]
T4 MII_RXCLK 36[16] RESERVED 36[20]
U7 MII_TX_CLK 36[24] RESERVED 36[28]
0x1A4 E2 N2HET2[3] 37[0] MIBSPI2CLK 37[4]
N3 N2HET2[7] 37[8] MIBSPI2NCS[0] 37[12]

4.2.2.1.1 Notes on Output Multiplexing

Table 4-27 lists the output signal multiplexing and control signals for selecting the desired functionality for each pad.

  • The pads default to the signal defined by the "Default Function" in Table 4-27.
  • The CTRL x columns in Table 4-27 contain a value of type x[y] which indicates the control register PINMMRx, bit y. It indicates the multiplexing control register and the bit that must be set in order to select the corresponding functionality to be output on any particular pad.
    • For example, consider the multiplexing on pin H3 for the 337-ZWT package:
      • 337
      ZWT
      BALL      		 DEFAULT FUNCTION CTRL1 OPTION 2 CTRL2 OPTION 3 CTRL3 OPTION 4 CTRL4 OPTION 5 CTRL5 OPTION 6 CTRL6
      H3 GIOA[6] 19[24] N2HET2[4] 19[26] ePWM1B 19[29]
    • When GIOA[6] is configured as an output pin in the GIO module control register, then the programmed output level appears on pin H3 by default. The PINMMR19[24] is set by default to indicate that the GIOA[6] signal is selected to be output.
    • If the application must output the N2HET2[4] signal on pin H3, it must clear PINMMR19[24] and set PINMMR19[26].
    • Note that the pin is connected as input to both the GIO and N2HET2 modules. That is, there is no input multiplexing on this pin.
  • The base address of the IOMM module starts at 0xFFFF_1C00. The Output mux control registers with the first register PINMMR0 starts at the offset address 0x110 within the IOMM module.

4.2.2.2 Input Multiplexing

Some signals are connected to more than one terminals, so that the inputs for these signals can come from either of these terminals. A multiplexor is implemented to let the application choose the terminal that will be used for providing the input signal from among the available options. The input path selection is done based on two bits in the PINMMR control registers as listed in Table 4-28.

Table 4-28 Input Multiplexing

Address Offset Signal Name Default Terminal Terminal 1 Input Multiplex Control Alternate Terminal Terminal 2 Input Multiplex Control
250h AD2EVT T10 PINMMR80[0] V10 PINMMR80[1]
25Ch GIOA[0] A5 PINMMR83[24] R5 PINMMR83[25]
260h GIOA[1] C2 PINMMR84[0] R6 PINMMR84[1]
GIOA[2] C1 PINMMR84[8] B15 PINMMR84[9]
GIOA[3] E1 PINMMR84[16] R7 PINMMR84[17]
GIOA[4] A6 PINMMR84[24] R8 PINMMR84[25]
264h GIOA[5] B5 PINMMR85[0] R9 PINMMR85[1]
GIOA[6] H3 PINMMR85[8] R10 PINMMR85[9]
GIOA[7] M1 PINMMR85[16] R11 PINMMR85[17]
GIOB[0] M2 PINMMR85[24] B8 PINMMR85[25]
268h GIOB[1] K2 PINMMR86[0] B16 PINMMR86[1]
GIOB[2] F2 PINMMR86[8] B9 PINMMR86[9]
GIOB[3] W10 PINMMR86[16] R4 PINMMR86[17]
GIOB[4] G1 PINMMR86[24] L17 PINMMR86[25]
26Ch GIOB[5] G2 PINMMR87[0] M17 PINMMR87[1]
GIOB[6] J2 PINMMR87[8] R3 PINMMR87[9]
GIOB[7] F1 PINMMR87[16] P3 PINMMR87[17]
MDIO F4 PINMMR87[24] G3 PINMMR87[25]
270h MIBSPI1NCS[4] U10 PINMMR88[0] N1 PINMMR88[1]
MIBSPI1NCS[5] U9 PINMMR88[8] P1 PINMMR88[9]
274h MII_COL W4 PINMMR89[16] F3 PINMMR89[17]
MII_CRS V4 PINMMR89[24] B4 PINMMR89[25]
278h MII_RX_DV U6 PINMMR90[0] B11 PINMMR90[1]
MII_RX_ER U5 PINMMR90[8] N19 PINMMR90[9]
MII_RXCLK T4 PINMMR90[16] K19 PINMMR90[17]
MII_RXD[0] U4 PINMMR90[24] P1 PINMMR90[25]
27Ch MII_RXD[1] T3 PINMMR91[0] A14 PINMMR91[1]
MII_RXD[2] U3 PINMMR91[8] G19 PINMMR91[9]
MII_RXD[3] V3 PINMMR91[16] H18 PINMMR91[17]
MII_TX_CLK U7 PINMMR91[24] D19 PINMMR91[25]
280h N2HET1[17] A13 PINMMR92[0] F3 PINMMR92[1]
N2HET1[19] B13 PINMMR92[8] G3 PINMMR92[9]
N2HET1[21] H4 PINMMR92[16] J3 PINMMR92[17]
N2HET1[23] J4 PINMMR92[24] G19 PINMMR92[25]
284h N2HET1[25] M3 PINMMR93[0] V5 PINMMR93[1]
N2HET1[27] A9 PINMMR93[8] B2 PINMMR93[9]
N2HET1[29] A3 PINMMR93[16] C3 PINMMR93[17]
N2HET1[31] J17 PINMMR93[24] W9 PINMMR93[25]
288h N2HET2[0] D6 PINMMR94[0] C1 PINMMR94[1]
N2HET2[1] D8 PINMMR94[8] D4 PINMMR94[9]
N2HET2[2] D7 PINMMR94[16] E1 PINMMR94[17]
N2HET2[3] E2 PINMMR94[24] D5 PINMMR94[25]
28Ch N2HET2[4] D13 PINMMR95[0] H3 PINMMR95[1]
N2HET2[5] D12 PINMMR95[8] D16 PINMMR95[9]
N2HET2[6] D11 PINMMR95[16] M1 PINMMR95[17]
N2HET2[7] N3 PINMMR95[24] N17 PINMMR95[25]
290h N2HET2[8] K16 PINMMR96[0] V2 PINMMR96[1]
N2HET2[9] L16 PINMMR96[8] K17 PINMMR96[9]
N2HET2[10] M16 PINMMR96[16] U1 PINMMR96[17]
N2HET2[11] N16 PINMMR96[24] C4 PINMMR96[25]
294h N2HET2[12] D3 PINMMR97[0] V6 PINMMR97[1]
N2HET2[13] D2 PINMMR97[8] C5 PINMMR97[9]
N2HET2[14] D1 PINMMR97[16] T1 PINMMR97[17]
N2HET2[15] K4 PINMMR97[24] C6 PINMMR97[25]
298h N2HET2[16] L4 PINMMR98[0] V7 PINMMR98[1]
N2HET2[18] N4 PINMMR98[8] E3 PINMMR98[9]
N2HET2[20] T5 PINMMR98[16] N2 PINMMR98[17]
N2HET2[22] T7 PINMMR98[24] N1 PINMMR98[25]
29Ch nTZ1_1 N19 PINMMR99[0] C3 PINMMR99[1]
nTZ1_2 F1 PINMMR99[8] B2 PINMMR99[9]
nTZ1_3 J3 PINMMR99[16] D19 PINMMR99[17]

4.2.2.2.1 Notes on Input Multiplexing

  • The Terminal x Input Multiplex Control column in Table 4-28 lists the multiplexing control register and the bit that must be set in order to select the terminal for providing the input signal to the system. For example, N2HET2[22] can appears on two different terminals at terminal number T7 and N1. By default PINMMR98[24] is set and PINMMR98[25] is cleared to select T7 for providing N2HET2[22] to the system. If the application chooses to use N1 for providing N2HET2[22] then PINMMR98[24] must be cleared and PINMMR98[25] must be set.
  • Base address of the IOMM module starts at 0xFFFF_1C00. Input mux control registers with the first register PINMMR80 starts at the offset address 0x250 within the IOMM module.

4.2.2.2.2 General Rules for Multiplexing Control Registers

  • The PINMMR control registers can only be written in privileged mode. A write in a nonprivileged mode will generate an error response.
  • If the application writes all 9’s to any PINMMR control register, then the default functions are selected for the affected pads.
  • Each byte in a PINMMR control register is used to select the functionality for a given pad. If the application sets more than one bit within a byte for any pad, then the default function is selected for this pad.
  • Several bits in the PINMMR control registers are reserved and are not used to enable any functions. If the application sets only these bits and clears the other bits, then the default functions are selected for the affected pads.

5 Specifications

5.1 Absolute Maximum Ratings(1)

Over Operating Free-Air Temperature Range
MIN MAX UNIT
Supply voltage VCC(2) –0.3 1.43 V
VCCIO, VCCP(2) –0.3 4.6
VCCAD –0.3 6.25
Input voltage All input pins, with exception of ADC pins –0.3 4.6 V
ADC input pins –0.3 6.25
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins, except AD1IN[31:0] and 		–20 20 mA
IIK (VI < 0 or VI > VCCAD)
AD1IN[31:0] and 		–10 10
Total –40 40
Operating free-air temperature (TA) –40 105 °C
Operating junction temperature (TJ) –40 130 °C
Storage temperature (Tstg) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds.

5.2 ESD Ratings

MIN MAX UNIT
VESD Electrostatic discharge (ESD) performance: Human Body Model (HBM) –2 2 kV
Charged Device Model (CDM) All pins except corner balls –500 500 V
Corner balls –750 750 V

5.3 Power-On Hours (POH)

POH is a function of voltage and temperature. Usage at higher voltages and temperatures will result in a reduction in POH to achieve the same reliability performance. The POH information in Table 5-1 is provided solely for convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI Semiconductor Products. To avoid significant device degradation, the device POH must be limited to those listed in Table 5-1. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207).

Table 5-1 Power-On Hours Limits

NOMINAL VCC VOLTAGE (V) JUNCTION
TEMPERATURE (TJ) 		LIFETIME POH(1)
1.2 V 105 ºC 100K
(1) POH represent device operation under the specified nominal conditions continuously for the duration of the calculated lifetime.

5.4 Device Recommended Operating Conditions(1)

MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCPLL PLL supply voltage 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD MibADC supply voltage 3 5.25 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD MibADC supply ground –0.1 0.1 V
VADREFHI Analog-to-Digital (A-to-D) high-voltage reference source VSSAD VCCAD V
VADREFLO A-to-D low-voltage reference source VSSAD VCCAD V
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature –40 130 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.

5.5 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 5-2 Clock Domain Timing Specifications

PARAMETER TEST CONDITIONS MIN MAX UNIT
fOSC OSC - oscillator clock frequency using an external crystal 5 20 MHz
fGCLK1 GCLK - R5F CPU clock frequency 330 MHz
fGCLK2 GCLK - R5F CPU clock frequency 330 MHz
fHCLK HCLK - System clock frequency 150 MHz
fVCLK VCLK - Primary peripheral clock frequency 110 MHz
fVCLK2 VCLK2 - Secondary peripheral clock frequency 110 MHz
fVCLK3 VCLK3 - Secondary peripheral clock frequency 150 MHz
fVCLKA1 VCLKA1 - Primary asynchronous peripheral clock frequency 110 MHz
fVCLKA2 VCLKA2 - Secondary asynchronous peripheral clock frequency 110 MHz
fVCLKA4 VCLKA4 - Secondary asynchronous peripheral clock frequency 110 MHz
fRTICLK1 RTICLK1 - clock frequency fVCLK MHz
fPROG/ERASE System clock frequency - flash programming/erase fHCLK MHz
fECLK External Clock 1 110 MHz
fETMCLKOUT ETM trace clock output 55 MHz
fETMCLKIN ETM trace clock input 110 MHz
fEXTCLKIN1 External input clock 1 110 MHz
fEXTCLKIN2 External input clock 2 110 MHz

Table 5-2 lists the maximum frequency of the CPU (GLKx), the level-2 memory (HCLK) and the peripheral clocks (VCLKx). It is not always possible to run each clock at its maximum frequency as GCLK must be an integral multiple of HCLK and HCLK must be an integral multiple of VCLKx. Depending on the system, the optimum performance may be obtained by maximizing either the CPU frequency, the level-two RAM interface, the level-two flash interface, or the peripherals.

5.6 Wait States Required - L2 Memories

Wait states are cycles the CPU must wait in order to retrieve data from the memories which have access times longer than a CPU clock. Memory wrapper, SCR interconnect and the CPU itself may introduce additional cycles of latency due to logic pipelining and synchronization. Therefore, the total latency cycles as seen by the CPU can be more than the number of wait states to cover the memory access time.

Figure 5-1 shows only the number of programmable wait states needed for L2 flash memory at different frequencies. The number of wait states is correlated to HCLK frequency. The clock ratio between CPU clock (GCLKx) and HCLK can vary. Therefore, the total number of wait states in terms of GCLKx can be obtained by taking the programmed wait states multiplied by the clock ratio.

There is no user programmable wait state for L2 SRAM access. L2 SRAM is clocked by HCLK and is limited to maximum 150 MHz.

RM57L843 wait_states_150MHz_new_pns195.gif Figure 5-1 Wait States Scheme

L2 flash is clocked by HCLK and is limited to maximum 150 MHz. The L2 flash can support zero data wait state up to 45 MHz.

5.7 Power Consumption Summary

Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP(3) MAX UNIT
ICC VCC digital supply and PLL current
(operating mode)		 fGCLK = 330 MHz,
fHCLK = 110 MHz,
fVCLK = 110 MHz,
fVCLK2 = 110 MHz,
fVCLK3 = 110 MHz 		595 880 (1) mA
VCC digital supply and PLL current
(LBIST mode, or PBIST mode)		 LBIST clock rate = 82.5 MHz 970 1350(2)(4) mA
PBIST ROM clock frequency = 55 MHz
ICCIO VCCIO digital supply current (operating mode) No DC load, VCCmax 15 mA
ICCAD VCCAD supply current (operating mode) Single ADC operational, VCCADmax 15 mA
Single ADC power down, VCCADmax 5 µA
Both ADCs operational, VCCADmax 30 mA
ICCREFHI ADREFHI supply current (operating mode) Single ADC operational, ADREFHImax 5 mA
Both ADCs operational, ADREFHImax 10 mA
ICCP VCCP pump supply current Read operation of two banks in parallel, VCCPmax 70 mA
Read from two banks and program or erase another bank, VCCPmax 93 mA
(1) The maximum ICC, value can be derated
  • linearly with voltage
  • by 1.7 mA/MHz for lower GCLK frequency when fGCLK= 3 * fHCLK= 3 * fVCLK
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    283 - 0.2 e 0.018TJK
(2) The maximum ICC, value can be derated
  • linearly with voltage
  • by 3.2 mA/MHz for lower GCLK frequency
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    283 - 0.2 e 0.018TJK
(3) The typical value is the average current for the nominal process corner and junction temperature of 25ºC.
(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator.

5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vhys Input hysteresis All inputs 180 mV
VIL Low-level input voltage All inputs(2) –0.3 0.8 V
VIH High-level input voltage All inputs(2) 2 VCCIO + 0.3 V
VOL Low-level output voltage IOL = IOLmax 0.2 * VCCIO V
IOL = 50 µA, standard output mode 0.2
VOH High-level output voltage IOH = IOHmax 0.8 * VCCIO V
IOH = 50 µA, standard output mode VCCIO – 0.3
IIC Input clamp current (I/O pins) VI < VSSIO – 0.3 or VI > VCCIO + 0.3 –3.5 3.5 mA
II Input current (I/O pins) IIH Pulldown 20 µA VI = VCCIO 5 40 µA
IIH Pulldown 100 µA VI = VCCIO 40 195
IIL Pullup 20 µA VI = VSS -40 –5
IIL Pullup 100 µA VI = VSS –195 –40
All other pins No pullup or pulldown –1 1
IOL Low-level output current Pins with output buffers of 8 mA drive strength VOLmax 8 mA
Pins with output buffers of 4 mA drive strength 4
Pins with output buffers of 2 mA drive strength 2
IOH High-level output current Pins with output buffers of 8 mA drive strength VOLmin –8 mA
Pins with output buffers of 4 mA drive strength –4
Pins with output buffers of 2 mA drive strength –2
CI Input capacitance 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.

5.9 Thermal Resistance Characteristics for the BGA Package (ZWT)

Over operating free-air temperature range (unless otherwise noted) (1)
°C / W
RΘJA Junction-to-free air thermal resistance, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 14.3
RΘJB Junction-to-board thermal resistance (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 5.49
RΘJC Junction-to-case thermal resistance (2s0p PCB) 5.02
ΨJT Junction-to-package top, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 0.29
ΨJB Junction-to-board, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 6.41
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report SPRA953

5.10 Timing and Switching Characteristics

5.10.1 Input Timings

RM57L843 ttl_inputs_pns160.gif Figure 5-2 TTL-Level Inputs

Table 5-3 Timing Requirements for Inputs(1)

MIN MAX UNIT
tpw Input minimum pulse width tc(VCLK) + 10(2) ns
tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.

5.10.2 Output Timings

Table 5-4 Switching Characteristics for Output Timings versus Load Capacitance (CL)

PARAMETER MIN MAX UNIT
Rise time, tr 8 mA low EMI pins CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 4 mA low EMI pins CL = 15 pF 5.6 ns
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, tf CL = 15 pF 5.6 ns
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Rise time, tr 2 mA-z low EMI pins CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Rise time, tr Selectable 8mA / 2mA-z pins 8 mA mode CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 2 mA-z mode CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
RM57L843 cmos_outputs_pns160.gif Figure 5-3 CMOS-Level Outputs

Table 5-5 Timing Requirements for Outputs(1)

MIN MAX UNIT
td(parallel_out) Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, for example, all signals in a GIOA port, or all N2HET1 signals, and so forth. 6 ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check for output buffer drive strength information on each signal.

 
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