ZHCSF90D August   2012  – June 2016 LP5560

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Single-Wire Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LED Driver Headroom Voltage
      2. 7.3.2 Single-Wire Interface
        1. 7.3.2.1 Run Command
        2. 7.3.2.2 Training Start Command
        3. 7.3.2.3 Training End Command
        4. 7.3.2.4 Run-Once Command
      3. 7.3.3 Training Mode
        1. 7.3.3.1 Ending the Training Sequence
        2. 7.3.3.2 Reset to Default
        3. 7.3.3.3 Changing the LED Current
        4. 7.3.3.4 Entering Follow Mode
        5. 7.3.3.5 Timeout
      4. 7.3.4 LED Output Current Setting
      5. 7.3.5 Rise and Fall Time Settings
      6. 7.3.6 LED ON-Time Setting
      7. 7.3.7 LED OFF-Time Setting
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Default Sequence
    6. 7.6 Registers
      1. 7.6.1 Control Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step-by-Step Design Procedure
        2. 8.2.2.2 Running the Default Blinking Sequence
        3. 8.2.2.3 Programming New Blinking Sequence to the Memory
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Voltage on VDD pin −0.3 6 V
Voltage on other pins (CTRL,LED)(4) −0.3 VDD + 0.3 V with 6 V maximum V
Continuous power dissipation(5) Internally Limited
Junction temperature, TJ-MAX 125 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Voltage
(4) Undervoltage lockout (UVLO) shuts down the LED driver with VIN drops to 2.3 V (typical). Power-on reset (POR) trips at VIN = 2 V (typical).
(5) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typical) and disengages at TJ=140°C (typical).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN NOM MAX UNIT
Voltage on power pin (VDD) 2.7 5.5 V
Junction temperature, TJ −30 125 °C
Ambient temperature, TA(1) −30 85 °C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(2) All voltages are with respect to the potential at the GND pin.

6.4 Thermal Information

THERMAL METRIC(1) LP5560 UNIT
YFQ (DSBGA)
4 PINS
RθJA Junction-to-ambient thermal resistance 184.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.8 °C/W
RθJB Junction-to-board thermal resistance 103.2 °C/W
ψJT Junction-to-top characterization parameter 9.1 °C/W
ψJB Junction-to-board characterization parameter 103.1 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 Electrical Characteristics

Unless otherwise specified: VIN = 3.6 V, CTRL = 3.6 V, VLED = 3.1 V; typical limits are for TA = 25°C, and minimum and maximum limits apply over the operating ambient temperature range (−30°C < TA < +85°C).(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISD Shutdown supply current CTRL = 0 V 0.4 0.75 µA
IQ Quiescent supply current ILED = 0 mA 25 30
ILED LED output current ISET = 0 2.26 2.8 3.34 mA
ISET = 1 (default) 4.61 5.3 5.99
ISET = 2 6.78 7.8 8.82
ISET = 3 8.87 10.2 11.53
ISET = 4 10.96 12.6 14.24
ISET = 5 13.5 15.0 16.5
ISET = 6 15.05 17.3 19.55
ISET = 7 16.96 19.5 22.04
ΔILED%/ΔVIN Line regulation 2.7 V ≤ VIN ≤ 4.5 V –3% 3% %/1V
IDX = 5.3 mA, Vƒ = 2.5 V
ΔILED%/ΔVLED(3) Load regulation 1.7 V ≤ VLED ≤ 3.4 V, ILED = 5.3 mA 0.6
VHR Headroom voltage(4) ILED = 5.3 mA 40 100 mV
ILED = 19.5 mA 40
VIH Logic input high level VIN = 2.7 V to 5.5 V 1.1 V
VIL Logic input low level VIN = 2.7 V to 5.5 V 0.6 V
ICTRL CTRL pin leakage current CTRL = 1.8 V 400 nA
T_cycle_H LED On time Adjustable(5), TA = 25°C 13.2 3009.6 ms
T_cycle_L LED OFF time 26.4 6019.2 ms
Trise LED current rise time(6) 0 1584 ms
Tfall LED current fall time(6) 0 1584 ms
Fade resolution Rise/fall time resolution See(5) 105.6 ms
(1) All voltages are with respect to the potential at the GND pins.
(2) Minimum and Maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm.
(3) ILED = LED output current, VLED = LED forward voltage.
(4) For LED output pin, headroom voltage is defined as the voltage across the internal current source when the LED current has dropped 10% from the value measured at VIN – 0.5 V. If headroom voltage requirement is not met, LED current regulation is compromised.
(5) Specified by design.
(6) LED current ramp-up and ramp-down uses a combined PWM-current adjustment.

6.6 Single-Wire Interface Timing Requirements

See (1)(2) and Figure 1
MIN MAX UNIT
TC_ON Command pulse on time 15 µs
TC_OFF Command pulse off time 30 µs
TT_ON Minimum training pulse on time(3) 200 µs
TT_OFF Minimum training pulse off time(4) 200 µs
TCAL Calibration pulse length 0.35 8 ms
T ENTER Command entering period 500 µs
T ENTER+T BLANK Command entering period + Blank period 1500 µs
(1) Specified by design.
(2) Minimum and Maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm.
(3) All CTRL signal high times between calibration pulse and training end are considered as training pulse on times.
(4) All CTRL signal low times between calibration pulse and training end are considered as training pulse off times.
LP5560 30172503.gif Figure 1. Interface Timing

6.7 Typical Characteristics

TJ = 25°C. Unless otherwise noted, typical characteristics apply to the Functional Block Diagram with: VIN = 3.6 V, RISET = 24 kΩ, CIN = 100 nF.
LP5560 30172521.gif
Figure 2. Standby Current vs VIN
LP5560 30172523.gif
5 mA
Figure 4. LED Current vs Input Voltage
LP5560 30172525.gif
5 mA
Figure 6. IOUT vs Headroom Voltage
LP5560 30172522.gif
Figure 3. Quiescent Current vs VIN
LP5560 30172524.gif
20 mA
Figure 5. LED Current vs Input Voltage
LP5560 30172526.gif
20 mA
Figure 7. IOUT vs Headroom Voltage